SLVS939B June   2009  – December 2014 TPS55332-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage (VIN)
      2. 7.3.2  Output Voltage (Vout)
      3. 7.3.3  Regulated Supply Voltage (VReg)
      4. 7.3.4  Over-Current Protection (SW)
      5. 7.3.5  Oscillator Frequency (RT)
      6. 7.3.6  Enable / Shutdown (EN)
      7. 7.3.7  Reset Delay (Cdly)
      8. 7.3.8  Reset Pin (RST)
      9. 7.3.9  Boost Capacitor (BOOT)
      10. 7.3.10 Soft Start (SS)
      11. 7.3.11 Synchronization (SYNC)
      12. 7.3.12 Regulation Voltage (VSENSE)
      13. 7.3.13 Reset Threshold (RST_TH)
      14. 7.3.14 Slew Rate Control (Rslew)
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Loop Control Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DCM Operation
      2. 7.4.2 CCM Operation
      3. 7.4.3 Loop Compensation For Stability Criteria
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Capacitor (Co)
        2. 8.2.2.2  Output Inductor Selection (Lo) for CCM
        3. 8.2.2.3  Output Diode
        4. 8.2.2.4  Input Capacitor CI
        5. 8.2.2.5  Output Voltage And Feedback Resistor Selection
        6. 8.2.2.6  Reset Threshold Resistor Selection
        7. 8.2.2.7  Soft Start Capacitor
        8. 8.2.2.8  Loop Compensation Calculation
        9. 8.2.2.9  Loop Compensation Response
        10. 8.2.2.10 Output Inductor Selection (LO) For DCM
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Inductor
      2. 10.1.2 Input Filter Capacitors
      3. 10.1.3 Feedback
      4. 10.1.4 Traces And Ground Plane
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PWP Package
20 Pins
(Top View)
p0021-03_lvs939.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
NC 1 NC Connect to ground
NC 2 NC Connect to ground
SYNC 3 I External synchronization clock input, 62-kΩ (typ) pull-down resistor
GND 4 I Connect to ground
EN 5 I Enable input, high voltage tolerant
RT 6 O Resistor to program internal oscillator frequency
Rslew 7 O Internal switch programmable slew rate control
RST 8 O Reset output open drain (active low)
Cdly 9 O Reset delay timer (programmed by external capacitor)
GND 10 O Analog ground, DVSS and SUB
SS 11 O Programmable soft-start. (external capacitor)
GND 12 I Connect to ground
RST_TH 13 I Input for RESET circuitry to detect undervoltage on output (adjustable threshold)
VSENSE 14 I Feedback input for voltage mode control
COMP 15 O Error amplifier output
VReg 16 I Internal low side FET to load output during start up or limit over shoot
PGND 17 O Power ground connection
SW 18 I/O Switched drain output/input
VIN 19 I Unregulated input voltage
BOOT 20 O Bootstrap capacitor pump