SLVSKU8 July   2026 TPS55285A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VCC Power Supply
      2. 6.3.2  Default Output Enable (OE) Bit Status
      3. 6.3.3  Input Undervoltage Lockout
      4. 6.3.4  Enable and Programmable UVLO
      5. 6.3.5  Soft Start
      6. 6.3.6  Shutdown and Load Discharge
      7. 6.3.7  Switching Frequency
      8. 6.3.8  Switching Frequency Dithering
      9. 6.3.9  Inductor Current Limit
      10. 6.3.10 Internal Charge Path
      11. 6.3.11 Output Voltage Setting
      12. 6.3.12 Output Current Limit
      13. 6.3.13 Output Cable Voltage Drop Compensation
      14. 6.3.14 Input Overvoltage Protection
      15. 6.3.15 Output Overvoltage Protection
      16. 6.3.16 Output Short-Circuit Protection
      17. 6.3.17 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power Save Mode
    5. 6.5 Programming
      1. 6.5.1 Data Validity
      2. 6.5.2 START and STOP Conditions
      3. 6.5.3 Byte Format
      4. 6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 6.5.5 Target Address and Data Direction Bit
      6. 6.5.6 Single Read and Write
      7. 6.5.7 Multi-Read and Multi-Write
  8. 7 Register Maps
    1. 7.1 REF Register (Address = 0h, 1h) [reset = 10100100b, 00000001b]
    2. 7.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100b]
    3. 7.3 VOUT_SR Register (Address = 3h) [reset = 00000001b]
    4. 7.4 VOUT_FS Register (Address = 4h) [reset = 00000011b]
    5. 7.5 CDC Register (Address = 5h) [reset = 11110000b]
    6. 7.6 MODE Register (Address = 6h) [reset = 00100000b]
    7. 7.7 STATUS Register (Address = 7h) [reset = 00000001b]
    8. 7.8 Register Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.3.4 Enable and Programmable UVLO

The TPS55285A has a dual function enable and undervoltage lockout (UVLO) circuit. When the input voltage at the VIN pin is above the input UVLO rising threshold of 3V and the EN/UVLO pin is pulled above EN logic high threshold VEH_H but less than the enable UVLO threshold VUVLO, the TPS55285A is enabled but still in standby mode. The TPS55285A starts to detect the resistance between MODE pin and ground. After that detection, the TPS55285A selects the I2C target address and default OE bit status accordingly.

The EN/UVLO pin has an accurate UVLO voltage threshold to support programmable input undervoltage lockout with hysteresis. When the EN/UVLO pin voltage is greater than the UVLO threshold of 1.05V, the TPS55285 is enabled for I2C communication and switching operation. A hysteresis current IUVLO_HYS is sourced out of the EN/UVLO pin to provide hysteresis that prevents on and off chattering in the presence of noise with a slowly changing input voltage.

By using resistor divider as shown in Figure 5-1, calculate the turn-on threshold using Equation 1.

Equation 1. TPS55285A

where

  • VUVLO is the UVLO threshold of 1.05V at the EN/UVLO pin

The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the EN/UVLO resistor divider and is calculated with Equation 2.

Equation 2. TPS55285A

where

  • IUVLO_HYS is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above VUVLO.

The EN/UVLO pin voltage must be less than 5.5V when using resistor divider to program the VIN UVLO threshold.

TPS55285A Programmable UVLO With Resistor Divider at the EN/UVLO PinFigure 6-1 Programmable UVLO With Resistor Divider at the EN/UVLO Pin

Using an NMOSFET together with a resistor divider implements both logic enable and programmable UVLO as shown in Figure 6-2. The EN logic high level needs to be greater than enable threshold plus the Vth of the NMOSFET Q1. The Q1 also eliminates the leakage current from VIN to ground through the UVLO resistor divider during shutdown mode.

TPS55285A Logic Enable and Programmable UVLOFigure 6-2 Logic Enable and Programmable UVLO

The external EN logic signal needs to follow the power-up sequencing shown in the Figure 6-3. The EN logic signal needs to go high after VIN rises (ramps up).

TPS55285A Power-Up Sequencing RequirementFigure 6-3 Power-Up Sequencing Requirement