ZHCSG55A November   2016  – February 2017 TPS54824

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-up into Pre-Biased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Inductor Selection
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Capacitor
        5. 8.2.2.5  Output Voltage Resistors Selection
        6. 8.2.2.6  Soft-start Capacitor Selection
        7. 8.2.2.7  Undervoltage Lockout Set Point
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  PGOOD Pull-up Resistor
        10. 8.2.2.10 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Alternate Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage VIN –0.3 19 V
BOOT –0.3 27
BOOT (10 ns transient) –0.3 30
BOOT (vs SW) –0.3 7
SW –1 20
SW (10 ns transient) –3 23
EN, SS/TRK, PGOOD, RT/CLK, FB, COMP –0.3 6.5
Operating Junction Temperature Range, TJ -40 150 °C
Storage Temperature Range, TSTG -55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
over operating free-air temperature range (unless otherwise noted)
Parameter MIN NOM MAX UNIT
VIN Input voltage range 4.5 17 V
VOUT Output Voltage 0.6 12 V
IOUT Output current 8 A
TJ Operating junction temperature -40 150 °C
fSW Switching Frequency (RT mode and PLL mode) 200 1600 kHz

6.4 Thermal Information

THERMAL METRIC(1) TPS54824 UNIT
RNV
18 PINS
ThetaJA Junction-to-ambient thermal resistance JEDEC 57.1 °C/W
ThetaJA Junction-to-ambient thermal resistance EVM 34 °C/W
ThetaJCtop Junction-to-case (top) thermal resistance 26.3 °C/W
ThetaJB Junction-to-board thermal resistance 18.8 °C/W
PsiJT Junction-to-top characterization parameter 0.8 °C/W
PsiJB Junction-to-board characterization parameter 18.8 °C/W
ThetaJCbot Junction-to-case (bottom) thermal resistance 1.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TJ = -40°C to 150°C, VIN = 4.5 V to 17 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE
UVLO_rise VIN under-voltage lockout V(VIN) rising 4.1 4.3 V
UVLO_fall V(VIN) falling 3.7 3.9 V
UVLO_hys Hysteresis VIN voltage 0.2 V
Ivin Operating non-switching supply current V(EN) = 5 V, V(FB) = 1.5 V 580 800 µA
Ivin_sdn Shutdown supply current V(EN) = 0 V 3 11 µA
ENABLE
Ven_rise EN threshold V(EN) rising 1.20 1.26 V
Ven_fall V(EN) falling 1.1 1.15 V
Ven_hys EN pin threshold voltage hysteresis 50 mV
Ip EN pin sourcing current V(EN) = 1.1V 1.2 µA
Iph EN pin sourcing current V(EN) = 1.3V 4.8 µA
Ih EN pin hysteresis current 3.6 µA
FB
VFB Regulated FB voltage TJ = 25°C 596 600 604 mV
595 600 605 mV
ERROR AMPLIFIER
gmea Error Amplifier Transconductance (gm) –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V 1100 µA/V
Error Amplifier DC gain 80 dB
Icomp_src Error Amplifier source current V(FB) = 0 V 100 µA
Icomp_snk Error Amplifier sink current V(FB) = 2 V -100 µA
gmps Power Stage Transconductance 16 A/V
SOFT-START
Iss Soft-start current 5 µA
V(SS/TRK) to V(FB) matching V(SS/TRK) = 0.4 V 25 mV
MOSFET
Rds(on)_h High-side switch resistance TA = 25°C, V(VIN) = 12 V 14.1 mΩ
TA = 25°C, V(VIN) = 4.5 V, V(BOOT-SW) = 4.5 V 15.9 mΩ
Rds(on)_l Low-side switch resistance TA = 25°C, V(VIN) = 12 V 6.1 mΩ
TA = 25°C, V(VIN) = 4.5 V 6.9 mΩ
BOOT UVLO Falling 2.2 2.6 V
CURRENT LIMIT
Ioc_HS_pk High-side peak current limit 10.8 12.9 15 A
Ioc_LS_snk Low-side sinking current limit –3.4 A
Ioc_LS_src Low-side sourcing current limit 9.3 11.4 13.6 A
RT/CLK
VIH Logic high input voltage 2 V
VIL Logic low input voltage 0.8 V
PGOOD
Power good threshold V(FB) rising (fault) 108%
V(FB) falling (good) 106%
V(FB) rising (good) 91%
V(FB) falling (fault) 89%
Ipg_lkg Leakage current when pulled high V(PGOOD) = 5 V 5 nA
Vpg_low PGOOD voltage when pulled low I(PGOOD) = 2 mA 0.3 V
Minimum VIN for valid output V(PGOOD) < 0.5 V, I(PGOOD) = 4 mA 0.7 1 V
Thermal protection
TTRIP Thermal protection trip point Temperature Rising 170 °C
THYST Thermal protection hysteresis 15 °C

6.6 Switching Characteristics

TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN
EN to start of switching 135 µs
PGOOD
Deglitch time PGOOD going high 272 Cycles
Deglitch time PGOOD going low 16 Cycles
SW
ton_min Minimum on time Measured at 50% to 50% of VIN, L = 0.68 µH, IOUT = 0.1 A 95 ns
toff_min Minimum off time (1) V(BOOT-SW) ≥ 2.6 V 0 ns
RT/CLK
fsw_min Minimum switching frequency (RT mode) R(RT/CLK) = 250 kΩ 200 kHz
Switching frequency (RT mode) R(RT/CLK) = 100 kΩ 450 500 550 kHz
fsw_max Maximum switching frequency (RT mode) R(RT/CLK) = 30.1 kΩ 1.6 MHz
fsw_clk Switching frequency synchronization range (PLL mode) 200 1600 kHz
RT/CLK falling edge to SW rising edge delay (PLL mode) Measure at 500kHz with RT resistor in series with RT/CLK 70 ns
HICCUP
Wait time before hiccup 512 Cycles
Hiccup time before restart 16384 Cycles
(1) Specified by design.

6.7 Timing Requirements

TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted)
MIN NOM MAX UNIT
RT/CLK
Minimum synchronization signal pulse width (PLL mode) 35 ns

6.8 Typical Characteristics

TPS54824 D002_SLVSDC9.gif
Figure 1. Efficiency for 9 V Input to 1 V Output
TPS54824 D004_SLVSDC9.gif
Figure 3. Efficiency for 12 V Input to 3.3 V Output
TPS54824 D006_slvsdc9.gif
V(EN) = 0.4 V
Figure 5. VIN Pin Shutdown Current vs Junction Temperature
TPS54824 D008_slvsdc9.gif
Figure 7. EN Pin Current vs Junction Temperature
TPS54824 D010_slvsdc9.gif
Figure 9. MOSFET Rds(on) vs Junction Temperature
TPS54824 D012_slvsdc9.gif
Figure 11. COMP to SW Transconductance vs Junction Temperature
TPS54824 D014_slvsdc9.gif
V(SS/TRK) = 0.4 V
Figure 13. SS/TRK to FB Offset vs Junction Temperature
TPS54824 D015_slvsdc9.gif
Figure 15. High-side Peak Current Limit vs Junction Temperature
TPS54824 D017_slvsdc9.gif
V(FB) = 0.6 V V(PGOOD) = 5 V
Figure 17. PGOOD Leakage Current vs Junction Temperature
TPS54824 D020_slvsdc9.gif
R(RT/CLK) = 100 kΩ
Figure 19. Switching Frequency vs Junction Temperature (500 kHz)
TPS54824 D023_slvsdc9.gif
Figure 21. Switching Frequency vs RT/CLK Resistor (Low Range)
TPS54824 D003_SLVSDC9.gif
Figure 2. Efficiency for 12 V Input to 1.5 V and 0.8 V Output
TPS54824 D005_slvsdc9.gif
V(EN) = 5 V V(FB) = 0.8 V
Figure 4. VIN Pin Nonswitching Supply Current vs Junction Temperature
TPS54824 D007_slvsdc9.gif
Figure 6. EN Pin Voltage Threshold vs Junction Temperature
TPS54824 D009_slvsdc9.gif
Figure 8. Regulated FB Voltage vs Junction Temperature
TPS54824 D011_slvsdc9.gif
Figure 10. Error Amplifier Transconductance vs Junction Temperature
TPS54824 D013_slvsdc9.gif
Figure 12. SS/TRK Current vs Junction Temperature
TPS54824 D022_slvsdc9.gif
Figure 14. FB voltage vs SS/TRK Voltage
TPS54824 D016_slvsdc9.gif
Figure 16. PGOOD Thresholds vs Junction Temperature
TPS54824 D018_slvsdc9.gif
VIN = 12 V L = 0.68 µH
Figure 18. Minimum on-time vs Ambient Temperature
TPS54824 D021_slvsdc9.gif
R(RT/CLK) = 30.1 kΩ
Figure 20. Switching Frequency vs Junction Temperature (1600 kHz)
TPS54824 D024_slvsdc9.gif
Figure 22. Switching Frequency vs RT/CLK Resistor (High Range)