ZHCSG12 February 2017 TPS54540B-Q1
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage | VIN | –0.3 | 65 | V |
| EN | –0.3 | 8.4 | ||
| FB | –0.3 | 3 | ||
| COMP | –0.3 | 3 | ||
| RT/CLK | –0.3 | 3.6 | ||
| BOOT-SW | –0.3 | 8 | ||
| SW | –0.6 | 65 | ||
| SW, 10-ns Transient | –2 | 65 | ||
| Operating junction temperature | –40 | 150 | °C | |
| Storage temperature, Tstg | –65 | 150 | °C | |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 | |||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VIN | Input supply voltage(1) | VO + Vdo | 60 | V | |
| VO | Output voltage | 0.8 | 58.8 | V | |
| IO | Output current | 0 | 5 | A | |
| TJ | Junction Temperature | –40 | 150 | °C | |
| THERMAL METRIC(1) | TPS54540B-Q1 | UNIT | |
|---|---|---|---|
| DDA (HSOP) | |||
| 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 41.7 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 52.7 | °C/W |
| RθJB | Junction-to-board thermal resistance | 22.6 | °C/W |
| ψJT | Junction-to-top characterization parameter | 7.9 | °C/W |
| ψJB | Junction-to-board characterization parameter | 22.5 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.6 | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE (VIN PIN) | |||||||
| Operating input voltage | 4.5 | 42 | V | ||||
| Internal undervoltage lockout threshold | Rising | 4.1 | 4.3 | 4.48 | V | ||
| Internal undervoltage lockout threshold hysteresis | 325 | mV | |||||
| Shutdown supply current | EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V | 2.25 | 4.5 | μA | |||
| Operating: nonswitching supply current | FB = 0.9 V, TA = 25°C | 146 | 175 | ||||
| ENABLE AND UVLO (EN PIN) | |||||||
| Enable threshold voltage | No voltage hysteresis, rising and falling | 1.1 | 1.2 | 1.3 | V | ||
| Input current | Enable threshold 50 mV | –4.6 | μA | ||||
| Enable threshold –50 mV | –0.58 | –1.2 | –1.8 | ||||
| Hysteresis current | –2.2 | –3.4 | –4.5 | μA | |||
| INTERNAL SOFT-START TIME | |||||||
| Soft-start time | fSW = 500 kHz, 10% to 90% | 2.1 | ms | ||||
| Soft-start time | fSW = 2.5 MHz, 10% to 90% | 0.42 | ms | ||||
| VOLTAGE REFERENCE | |||||||
| Voltage reference | 0.792 | 0.8 | 0.808 | V | |||
| HIGH-SIDE MOSFET | |||||||
| On-resistance | VIN = 12 V, BOOT-SW = 6 V | 92 | 190 | mΩ | |||
| ERROR AMPLIFIER | |||||||
| Input current | 50 | nA | |||||
| Error amplifier transconductance (gM) | –2 μA < ICOMP < 2 μA, VCOMP = 1 V | 350 | μS | ||||
| Error amplifier transconductance (gM) during soft-start | –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V | 77 | μS | ||||
| Error amplifier DC gain | VFB = 0.8 V | 10000 | V/V | ||||
| Minimum unity gain bandwidth | 2500 | kHz | |||||
| Error amplifier source and sink | V(COMP) = 1 V, 100-mV overdrive | ±30 | μA | ||||
| COMP to SW current transconductance | 17 | A/V | |||||
| CURRENT LIMIT | |||||||
| Current limit threshold | All VIN and temperatures, Open Loop | 6.3 | 7.9 | 9.5 | A | ||
| All temperatures, VIN = 12 V, Open Loop | 6.3 | 7.9 | 9.5 | ||||
| VIN = 12 V, TA = 25°C, Open Loop(1) | 7.0 | 7.9 | 8.8 | ||||
| THERMAL SHUTDOWN | |||||||
| Thermal shutdown | 176 | °C | |||||
| Thermal shutdown hysteresis | 12 | °C | |||||
| ERROR AMPLIFIER | |||||||
| Enable to COMP active | VIN = 12 V, TA = 25°C | 346 | µs | ||||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| RT/CLK | |||||
| Minimum CLK input pulse width | 15 | ns | |||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| CURRENT LIMIT | ||||||
| Current limit threshold delay | 60 | ns | ||||
| RT/CLK | ||||||
| Switching frequency range using RT mode | 100 | 2500 | kHz | |||
| fSW | Switching frequency | RT = 200 kΩ | 450 | 500 | 550 | kHz |
| Switching frequency range using CLK mode | 160 | 2300 | kHz | |||
| RT/CLK high threshold | 1.55 | 2 | V | |||
| RT/CLK low threshold | 0.5 | 1.2 | V | |||
| RT/CLK falling edge to SW rising edge delay | Measured at 500 kHz with RT resistor in series | 55 | ns | |||
| PLL lock in time | Measured at 500 kHz | 78 | μs | |||