8.3.1 Fixed Frequency PWM Control

The TPS54418A device uses an adjustable fixed-frequency peak-current-mode control. The output voltage is compared through external resistors on the VSENSE to pin an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output is compared to the high-side power-switch current. When the power switch reaches the COMP voltage, the high-side power switch is turned off and the low-side power switch is turned on.

The COMP pin voltage increases and decreases as the peak switch current increases and decreases. The device implements a current-limit function by clamping the COMP pin voltage to a maximum value, which limits the maximum peak current the device supplies. The device also implements a minimum COMP pin voltage clamp for improved transient response. When the COMP pin voltage is pushed low to the minimum clamp, such as during a load release event, turn-on of the high-side power switch is inhibited.

8.3.2 Slope Compensation and Output Current

The TPS54418A device adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full duty cycle range.

8.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation

The TPS54418A device has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics overtemperature and voltage.

To improve drop out, the TPS54418A device is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.5 V. The high-side MOSFET is turned off using an UVLO circuit, allowing for the low-side MOSFET to conduct when the voltage from BOOT to PH drops below 2.5 V. Because the supply current sourced from the BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high.

8.3.4 Error Amplifier

The TPS54418A device has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS pin voltage or the internal 0.8 V voltage reference. The transconductance of the error amplifier is 225 μA/V during normal operation. When the voltage of VSENSE pin is below 0.8 V and the device is regulating using the SS voltage, the transconductance is 70 μA/V. The frequency compensation components are placed between the COMP pin and ground.

8.3.5 Voltage Reference

The voltage reference system produces a precise ±1% voltage reference overtemperature by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits produce 0.8 V at the non-inverting input of the error amplifier.

8.3.6 Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use divider resistors with 1% tolerance or better. Start with a value of 100 kΩ for the R1 resistor and use Equation 1 to calculate R2. To improve efficiency at very light loads, consider using larger resistor values. If the values are too high, the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.

Equation 1.

Figure 23. Voltage Divider Circuit

8.3.7 Enable and Adjusting Undervoltage Lockout

The TPS54418A device is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher under-voltage lockout (UVLO), use the EN pin as shown in Figure 24 to adjust the input voltage UVLO by using two external resistors. It is recommended to use the enable resistors to set the UVLO falling threshold (V_STOP) above 2.7 V. The rising threshold (V_START) should be set to provide enough hysteresis to allow for any input supply variations. The EN pin has an internal pull-up current source that provides the default condition of the TPS54418A device operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.55 μA of hysteresis is added. When the EN pin is pulled below 1.18 V, the 2.55 μA is removed. This additional current facilitates input voltage hysteresis.

Figure 24. Adjustable Undervoltage Lockout

Equation 2.

Equation 3.

8.3.8 Soft-Start Pin

The TPS54418A device regulates to the lower of the SS pin and the internal reference voltage. A capacitor on the SS pin to ground implements a soft-start time. The TPS54418A device has an internal pull-up current source of 1.8 μA which charges the external soft-start capacitor. Equation 4 calculates the required soft-start capacitor value where t_SS is the desired soft-start time in ms, I_SS is the internal soft-start charging current of 1.8 μA, and V_REF is the internal voltage reference of 0.8 V. it is recommended to maintain the soft-start time in the range between 1 ms and 10 ms.

Equation 4.

where

• C_SS is in nF
• t_SS is in ms
• I_SS is in µA
• V_REF is in V

If during normal operation, the input voltage goes below the UVLO, EN pin pulled below 1.2 V, or a thermal shutdown event occurs, the TPS54418A device stops switching and the SS is discharged to 0 volts before reinitiating a powering up sequence.

8.3.9 Sequencing

Many of the common power supply sequencing methods can be implemented using the SS, EN and PWRGD pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin of another device. Figure 25 shows the sequential method. The power good is coupled to the EN pin on the TPS54418A device which enables the second power supply once the primary supply reaches regulation.

Ratiometric start up can be accomplished by connecting the SS pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time the pull up current source must be doubled in Equation 4. The ratiometric method is shown in Figure 27.

Figure 25. Sequencial Start-Up Schematic

Figure 26. Sequential Startup using EN and PWRGD

Figure 27. Ratiometric Start-Up Schematic

Figure 28. Ratiometric Start-Up Using Coupled SS Pins

8.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)

The switching frequency of the TPS54418A device is adjustable over a wide range from 200 kHz to 2000 kHz by placing a maximum of 1000 kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 5 or Figure 6 or Equation 5.

Equation 5.

where

• R_RT is in kΩ
• f_SW is in kHz

Equation 6.

where

• R_RT is in kΩ
• f_SW is in kHz

To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the efficiency, maximum input voltage and minimum controllable on time should be considered.

The minimum controllable on time is typically 60 ns at full current load and 110 ns at no load, and limits the maximum operating input voltage or output voltage.

8.3.11 Overcurrent Protection

The TPS54418A device implements a cycle-by-cycle current limit. During each switching cycle the high-side switch current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally. This clamp functions as a switch current limit.

8.3.12 Frequency Shift

To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54418A device implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the low-side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%, then 75%, then 50%, then 25% as the voltage decreases from 0.8 to 0 volts on VSENSE pin to allow the low-side MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increases as the voltage on VSENSE increases from 0 to 0.8 volts. See Figure 7 for details.

8.3.13 Reverse Overcurrent Protection

The TPS54418A device implements low-side current protection by detecting the voltage across the low-side MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side MOSFET if the reverse current is more than 1.3 A. By implementing this additional protection scheme, the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased outputs.

8.3.14 Synchronize Using the RT/CLK Pin

The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 29. To implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least 75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V typically. The recommended synchronization frequency range is 300 kHz to 2000 kHz. If the external system clock is to be removed, TI recommends that it be removed on the falling edge of the clock.

.
.

Figure 29. Synchronizing to a System Clock

Figure 30. Plot of Synchronizing to System Clock

8.3.15 Power Good (PWRGD Pin)

The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is recommended to use a pull-up resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.2 V.

8.3.16 Overvoltage Transient Protection

The TPS54418A device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high-side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold the high-side MOSFET is allowed to turn on the next clock cycle.

8.3.17 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 160°C, the device reinitiates the power up sequence by discharging the SS pin to 0 volts. The thermal shutdown hysteresis is 15°C.

8.4.1 Small Signal Model for Loop Response

Figure 31 shows an equivalent model for the TPS54418A device control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a g_M of 225 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor R_OUT(ea) and capacitor C_OUT(ea) model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the R_LOAD with a current source with the appropriate load step amplitude and step rate in a time domain analysis.

Figure 31. Small Signal Model for Loop Response

8.4.2 Simple Small Signal Model for Peak Current Mode Control

Figure 32 is a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54418A device power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 7 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 31) is the power stage transconductance. The g_M for the TPS54418A device is 13 A/V. The low frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 8. As the load current increases and decreases, the low frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with load current [see Equation 9]. The combined effect is highlighted by the dashed line in the right half of Figure 33. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation.

Figure 32. Simple Small Signal Model

Figure 33. Frequency Response

Equation 7.

Equation 8.

Equation 9.

Equation 10.

8.4.3 Small Signal Model for Frequency Compensation

The TPS54418A device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 34. The Type-II circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In Type-IIA, one additional high frequency pole is added to attenuate high-frequency noise.

Figure 34. Types of Frequency Compensation

The design guidelines for TPS54418A device loop compensation are as follows:

1. Calculate the modulator pole (f_P(MOD)) and the esr zero, (f_Z1) using Equation 11 and Equation 12. If the output voltage is a high percentage of the capacitor rating it may be necessary to derate the output capacitor (C_OUT). Use the capacitor manufacturer information to derate the capacitor value. Use Equation 13 and Equation 14 to estimate a starting point for the crossover frequency, f_C. Equation 13 shows the geometric mean of the modulator pole and the ESR zero and Equation 14 is the mean of modulator pole and the switching frequency. Use the lower value of Equation 13 or Equation 14 as the maximum crossover frequency.
Equation 11.
Equation 12.
Equation 13.
Equation 14.
2. Calculate resistor R3. Equation 15 shows the calculation for resistor R3.
Equation 15.
where
• g_M(ea) is the amplifier gain (225 μA/V)
• g_M(ps) is the power stage gain (13 A/V)
3. Place a compensation zero at the dominant pole. f_P. Equation 16 shows the calculation for capacitor C1.
Equation 16.
Equation 17.
4. Capacitor C2 is optional. It can be used to cancel the zero from the output capacitor (C_OUT) ESR.
Equation 18.