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  • 具有 Eco-Mode™ 的 TPS54360 60V 输入、3.5A、降压直流/直流转换器

    • ZHCSA92G August   2012  – June 2018 TPS54360

      PRODUCTION DATA.  

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  • 具有 Eco-Mode™ 的 TPS54360 60V 输入、3.5A、降压直流/直流转换器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      效率与负载电流间的关系
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft-Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
      11. 7.3.11 Synchronization to RT/CLK Terminal
      12. 7.3.12 Overvoltage Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small Signal Model for Loop Response
      15. 7.3.15 Simple Small Signal Model for Peak Current Mode Control
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VIN = < 4.5 V (Minimum VIN)
      2. 7.4.2 Operation with EN Control
      3. 7.4.3 Alternate Power Supply Topologies
        1. 7.4.3.1 Inverting Power
        2. 7.4.3.2 Split-Rail Power Supply
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection (LO)
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Catch Diode
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Minimum VIN
        11. 8.2.2.11 Compensation
        12. 8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
        13. 8.2.2.13 Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Estimated Circuit Area
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 使用 WEBENCH® 工具定制设计方案
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
  12. 12机械、封装和可订购信息
  13. 重要声明

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DATA SHEET

具有 Eco-Mode™ 的 TPS54360 60V 输入、3.5A、降压直流/直流转换器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 4.5V 到 60V（绝对最大值为 65V）输入范围
  • 3.5A 持续电流、4.5A 最低峰值电感器电流限制
  • 电流模式控制直流/直流转换器
  • 92mΩ 高侧金属氧化物半导体场效应晶体管 (MOSFET)
  • 轻负载条件下使用脉冲跳跃实现的高效率 Eco-mode。™
  • 轻负载条件下使用集成型引导 (BOOT) 再充电场效应晶体管 (FET) 实现的低压降
  • 146μA 静态工作电流
  • 2μA 关断电流
  • 100kHz 至 2.5MHz 的固定开关频率
  • 同步至外部时钟
  • 可调欠压闭锁 (UVLO) 电压和滞后
  • 内部软启动
  • 精确逐周期电流限制
  • 过热、过压和频率折返保护
  • 0.8V 1% 内部电压基准
  • 8 引脚 HSOIC，配备 PowerPAD™封装
  • -40°C 至 150°C TJ 运行范围
  • 使用 TPS54360 并借助 WEBENCH® 电源设计器创建定制设计方案增加了 WEBENCH 信息

2 应用

    12V，24V 和 48V 工业、汽车和通信电源系统

3 说明

TPS54360 是一款具有集成型高侧 MOSFET 的 60V、3.5A 降压稳压器。按照 ISO 7637 标准，此器件能够耐受的抛负载脉冲高达 65V。电流模式控制提供了简单的外部补偿和灵活的组件选择。一个低纹波脉冲跳跃模式将无负载时的电源电流减小至 146μA。当启用引脚被拉至低电平时，关断电源电流被减少至 2μA。

欠压闭锁在内部设定为 4.3V，但可用使能引脚将之提高。该器件可在内部控制输出电压启动斜坡，从而控制启动过程并消除过冲。

宽开关频率范围可实现对效率或者外部组件尺寸的优化。频率折返和热关断功能在过载情况下保护内部和外部组件不受损坏。

TPS54360 可提供 8 引脚热增强型 HSOIC PowerPAD™封装。

器件信息

订货编号 封装 封装尺寸
TPS54360 HSOIC (8) 4.89mm × 3.90mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

空白

Device Images

简化电路原理图

TPS54360 simple_sch_lvsBB4.gif

效率与负载电流间的关系

TPS54360 eff_fron_pg_lvsbb4.gif

4 修订历史记录

Changes from F Revision (March 2017) to G Revision

  • Added TI 参考设计顶部导航图标 Go
  • Added VBOOT clamping stipulation to Equation 2Go

Changes from E Revision (March 2014) to F Revision

  • 在特性、详细设计流程和器件支持部分Go
  • Changed the Handling Ratings table to the ESD Ratings tableGo
  • Moved the Storage temperature to the Absolute Maximum Ratings tableGo
  • Changed VIN MIN Value From: 4.5 V To: VO + VDO, and added Note 1 in the Recommended Operating ConditionsGo
  • Updated text and added Equation 1 and Equation 2 in Low Dropout Operation and Bootstrap Voltage (BOOT)Go
  • Deleted text: "The start and stop voltage for a typical 5 V..." and Figure: "5V Start/Stop Voltage" from the Low Dropout Operation and Bootstrap Voltage (BOOT) sectionGo
  • Changed Equation 7 and Equation 8Go
  • Changed Equation 27Go
  • Added new section: Minimum VINGo
  • Deleted 2 graphs named "Low Dropout Operation" from the Application Curves sectionGo

Changes from D Revision (February 2013) to E Revision

  • 将数据表更改成了全新的 TI 版面布局并增加了器件信息表Go
  • Added the Handling Ratings table and Recommended Operating Conditions tableGo
  • Changed the Operating: nonswitching supply current TEST CONDITIONS From: FB = 0.83 V To: FB = 0.9 V Go
  • Changed RT/CLK high threshold MAX value From: 1.7 V To: 2 V Go
  • Changed Figure 6 title From: HIGH FREQUENCY RANGE To: LOW FREQUENCY RANGEGo
  • Changed Figure 7 title From: LOW FREQUENCY RANGE To: HIGH FREQUENCY RANGEGo

Changes from C Revision (October 2012) to D Revision

  • Changed Figure 11 and Figure 12 From: IEN (µV) To: IEN (µA)Go

Changes from B Revision (September 2012) to C Revision

  • Changed From: 20 mV/div To: 200 mV/div in Figure 42Go

Changes from A Revision (September 2012) to B Revision

  • 功能从“1μA 关断电流”更改为“2μA 关断电流”Go

Changes from * Revision (August 2012) to A Revision

  • 将器件状态从“产品预览”更改成了“生产数据”Go

5 Pin Configuration and Functions

DDA Package
8-Pin HSOIC
(Top View)
TPS54360 powerpad.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 1 O A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high side MOSFET, the output is switched off until the capacitor is refreshed.
VIN 2 I Input supply voltage with 4.5 V to 60 V operating range.
EN 3 I Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
RT/CLK 4 I Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB 5 I Inverting input of the transconductance (gm) error amplifier.
COMP 6 O Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this terminal.
GND 7 – Ground
SW 8 I The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad 9 – GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper operation.

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage VIN –0.3 65 V
EN –0.3 8.4
BOOT 73
FB –0.3 3
COMP –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-SW 8 V
SW –0.6 65
SW, 10-ns transient –2 65
Operating junction temperature –40 150 °C
Storage temperature, TSTG –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

MAX UNIT
VESD(1) Human Body Model (HBM) ESD Stress Voltage (2) ±2000 V
Charged Device Model (HBM) ESD Stress Voltage (3) ±500 V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. terminals listed as 1000 V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. terminals listed as 250 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage(1) VO + VDO 60 V
VO Output voltage 0.8 58.8 V
IO Output current 0 3.5 A
TJ Junction temperature –40 150 °C
(1) See Equation 1

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS54360 UNIT
DDA (HSOIC)
8 PINS
θJA Junction-to-ambient thermal resistance (standard board) 42.0 °C/W
ψJT Junction-to-top characterization parameter 5.9 °C/W
ψJB Junction-to-board characterization parameter 23.4 °C/W
θJCtop Junction-to-case(top) thermal resistance 45.8 °C/W
θJCbot Junction-to-case(bottom) thermal resistance 3.6 °C/W
θJB Junction-to-board thermal resistance 23.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 4.5 to 60V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN TERMINALS)
Operating input voltage 4.5 60 V
Internal undervoltage lockout threshold Rising 4.1 4.3 4.48 V
Internal undervoltage lockout threshold hysteresis 325 mV
Shutdown supply current EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V 2.25 4.5 μA
Operating: nonswitching supply current FB = 0.9 V, TA = 25°C 146 175
ENABLE AND UVLO (EN TERMINALS)
Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V
Input current Enable threshold +50 mV –4.6 μA
Enable threshold –50 mV –0.58 –1.2 -1.8
Hysteresis current –2.2 –3.4 -4.5 μA
VOLTAGE REFERENCE
Voltage reference 0.792 0.8 0.808 V
HIGH-SIDE MOSFET
On-resistance VIN = 12 V, BOOT-SW = 6 V 92 190 mΩ
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 350 μMhos
Error amplifier transconductance (gM) during soft-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V 77 μMhos
Error amplifier dc gain VFB = 0.8 V 10,000 V/V
Min unity gain bandwidth 2500 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±30 μA
COMP to SW current transconductance 12 A/V
CURRENT LIMIT
Current limit threshold All VIN and temperatures, Open Loop(1) 4.5 5.5 6.8 A
All temperatures, VIN = 12 V, Open Loop(1) 4.5 5.5 6.25
VIN = 12 V, TA = 25°C, Open Loop(1) 5.2 5.5 5.85
Current limit threshold delay 60 ns
THERMAL SHUTDOWN
Thermal shutdown 176 °C
Thermal shutdown hysteresis 12 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINALS)
Switching frequency range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 500 550 kHz
Switching frequency range using CLK mode 160 2300 kHz
RT/CLK high threshold 1.55 2 V
RT/CLK low threshold 0.5 1.2 V
(1) Open Loop current limit measured directly at the SW terminal and is independent of the inductor value and slope compensation.

6.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL SOFT-START TIME
Soft-start time fSW = 500 kHz, 10% to 90% 2.1 ms
Soft-start time fSW = 2.5 MHz, 10% to 90% 0.42 ms
HIGH-SIDE MOSFET
Minimum controllable on time VIN = 12 V, TA = 25°C 135 ns
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINALS)
Minimum CLK input pulse width 15 ns
RT/CLK falling edge to SW rising edge delay Measured at 500 kHz with RT resistor in series 55 ns
PLL lock in time Measured at 500 kHz 78 μs

6.7 Typical Characteristics

TPS54360 G001_SLVSBB4.png
Figure 1. On Resistance vs Junction Temperature
TPS54360 G003_SLVSBB4.png
Figure 3. Switch Current Limit vs Junction Temperature
TPS54360 G002_SLVSBB4.png
Figure 2. Voltage Reference vs Junction Temperature
TPS54360 G004_SLVSBB4.png
Figure 4. Switch Current Limit vs Input Voltage
TPS54360 G005_SLVSBB4.png
Figure 5. Switching Frequency vs Junction Temperature
TPS54360 G007_SLVSBB4.png
Figure 7. Switching Frequency vs RT/CLK Resistance
High Frequency Range
TPS54360 G009_SLVSBB4.png
Figure 9. EA Transconductance During Soft-Start vs Junction Temperature
TPS54360 G011_SLVSBB4.gif
Figure 11. EN Terminal Current vs Junction Temperature
TPS54360 G0112a_SLVSBB4.png
Figure 13. EN Terminal Current Hysteresis vs Junction Temperature
TPS54360 G014_SLVSBB4.png
Figure 15. Shutdown Supply Current vs Junction Temperature
TPS54360 G016_SLVSBB4.png
Figure 17. VIN Supply Current vs Junction Temperature
TPS54360 G018_SLVSBB4.png
Figure 19. BOOT-SW UVLO vs Junction Temperature
TPS54360 G021_SLVSBB4.gif
Figure 21. Soft-Start Time vs Switching Frequency
TPS54360 G006_SLVSBB4.png
Figure 6. Switching Frequency vs RT/CLK Resistance
Low Frequency Range
TPS54360 G008_SLVSBB4.png
Figure 8. EA Transconductance vs Junction Temperature
TPS54360 G010_SLVSBB4.png
Figure 10. EN Terminal Voltage vs Junction Temperature
TPS54360 G012_SLVSBB4.gif
Figure 12. EN Terminal Current vs Junction Temperature
TPS54360 G013_SLVSBB4.png
Figure 14. Switching Frequency vs FB
TPS54360 G015_SLVSBB4.png
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
TPS54360 G017_SLVSBB4.png
Figure 18. VIN Supply Current vs Input Voltage
TPS54360 G019_SLVSBB4.png
Figure 20. Input Voltage UVLO vs Junction Temperature

7 Detailed Description

7.1 Overview

The TPS54360 is a 60-V, 3.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. The device implements constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows either efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground connected to the RT/CLK terminal. The device has an internal phase-locked loop (PLL) connected to the RT/CLK terminal that will synchronize the power switch turn on to a falling edge of an external clock signal.

The TPS54360 has a default input start-up voltage of approximately 4.3 V. The EN terminal can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up current source enables operation when the EN terminal is floating. The operating current is 146 μA under no load condition (not switching). When the device is disabled, the supply current is 2 μA.

The integrated 92mΩ high side MOSFET supports high efficiency power supply designs capable of delivering 3.5 amperes of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is supplied by a bootstrap capacitor connected from the BOOT to SW terminals. The TPS54360 reduces the external component count by integrating the bootstrap recharge diode. The BOOT terminal capacitor voltage is monitored by a UVLO circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54360 to operate at high duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the application. The minimum output voltage is the internal 0.8 V feedback reference.

Output overvoltage transients are minimized by an overvoltage transient protection (OVP) comparator. When the OVP comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is less than 106% of the desired output voltage.

The TPS54360 includes an internal soft-start circuit that slows the output rise time during start-up to reduce in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help maintain control of the inductor current.

7.2 Functional Block Diagram

TPS54360 fbd_slvsbx7.gif

7.3 Feature Description

7.3.1 Fixed Frequency PWM Control

The TPS54360 uses fixed frequency, peak current mode control with adjustable switching frequency. The output voltage is compared through external resistors connected to the FB terminal to an internal voltage reference by an error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output at the COMP terminal controls the high side power switch current. When the high side MOSFET switch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP terminal voltage will increase and decrease as the output current increases and decreases. The device implements current limiting by clamping the COMP terminal voltage to a maximum level. The pulse skipping Eco-mode is implemented with a minimum voltage clamp on the COMP terminal.

7.3.2 Slope Compensation Output Current

The TPS54360 adds a compensating ramp to the MOSFET switch current sense signal. This slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.

7.3.3 Pulse Skip Eco-mode

The TPS54360 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.

When in Eco-mode, the COMP terminal voltage is clamped at 600 mV and the high side MOSFET is inhibited. Since the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the COMP terminal voltage. The high side MOSFET is enabled and switching resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.

During Eco-mode operation, the TPS54360 senses and controls peak switch current, not the average load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor value. The circuit in Figure 34 enters Eco-mode at about 24 mA output current. As the load current approaches zero, the device enters a pulse skip mode during which it draws only 146 μA input quiescent current.

7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54360 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW terminals provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended for stable performance over temperature and voltage.

When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54360 will operate at 100% duty cycle as long as the BOOT to SW terminal voltage is greater than 2.1 V. When the voltage from BOOT to SW drops below 2.1 V, the high side MOSFET is turned off and an integrated low side MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high output voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.

Because the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode voltage and the printed circuit board resistance.

Equation 1 calculates the minimum input voltage required to regulate the output voltage and ensure normal operation of the device. This calculation must include tolerance of the component specifications and the variation of these specifications at their maximum operating temperature in the application.

Equation 1. TPS54360 q_Vin_min_slvsbb4.gif

where

  • VF = Schottky diode forward voltage
  • Rdc = DC resistance of inductor and PCB
  • RDS(on) = High-side MOSFET RDS(on)

At heavy loads, the minimum input voltage must be increased to ensure a monotonic start- up. Use Equation 2 to calculate the minimum input voltage for this condition.

Equation 2. TPS54360 q_vout(max)_lvsBN0.gif

where

  • D(max) ≥ 0.9
  • IB2SW = 100 µA
  • tSW = 1 / fSW(MHz)
  • VB2SW = VBOOT + VF
  • VBOOT = (1.41 × VIN – 0.554 – VF / tSW – 1.847 × 103 × IB2SW) / (1.41 + 1 / tSW)*
  • RDS(on) = 1 / (–0.3 × VB2SW2 + 3.577 × VB2SW – 4.246)

7.3.5 Error Amplifier

The TPS54360 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier compares the FB terminal voltage to the lower of the internal soft-start voltage or the internal 0.8 V voltage reference. The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-start voltage.

The frequency compensation components (capacitor, series resistor and capacitor) are connected between the error amplifier output COMP terminal and GND terminal.

7.3.6 Adjusting the Output Voltage

The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor divider from the output node to the FB terminal. It is recommended to use 1% tolerance or better divider resistors. Select the low side resistor RLS for the desired divider current and use Equation 3 to calculate RHS. To improve efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable.

Equation 3. TPS54360 eq1_Rhs_lvsbb4.gif

7.3.7 Enable and Adjusting Undervoltage Lockout

The TPS54360 is enabled when the VIN terminal voltage rises above 4.3 V and the EN terminal voltage exceeds the enable threshold of 1.2 V. The TPS54360 is disabled when the VIN terminal voltage falls below 4 V or when the EN terminal voltage is below 1.2 V. The EN terminal has an internal pull-up current source, I1, of 1.2 μA that enables operation of the TPS54360 when the EN terminal floats.

If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to adjust the input voltage UVLO with two external resistors. When the EN terminal voltage exceeds 1.2 V, an additional 3.4 μA of hysteresis current, Ihys, is sourced out of the EN terminal. When the EN terminal is pulled below 1.2 V, the 3.4 μA Ihys current is removed. This addional current facilitates adjustable input voltage UVLO hysteresis. Use Equation 4 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 5 to calculate RUVLO2 for the desired VIN start voltage.

In applications designed to start at relatively low input voltages (e.g., from 4.5 V to 9 V) and withstand high input voltages (e.g., from 40 V to 60 V), the EN terminal may experience a voltage greater than the absolute maximum voltage of 8.4 V during the high input voltage condition. It is recommended to use a zener diode to clamp the terminal voltage below the absolute maximum rating.

TPS54360 adj_uv_loclout_lvsbb4.gifFigure 22. Adjustable Undervoltage Lockout (UVLO)
Equation 4. TPS54360 q_uvlo1_lvsbb4.gif
Equation 5. TPS54360 q_uvlo2_lvsbb4.gif

 
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