SLVS919C January   2009  – September 2015 TPS54060

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Resistor and External Clock (RT/CLK Pin) Timing Requirements
    7. 6.7 Timing Resistor and External Clock (RT/CLK PIN) Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Slow Start/Tracking Pin (SS/TR)
      8. 7.3.8  Overload Recovery Circuit
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      10. 7.3.10 Overcurrent Protection and Frequency Shift
      11. 7.3.11 Power Good (PWRGD Pin)
      12. 7.3.12 Overvoltage Transient Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small Signal Model for Loop Response
      15. 7.3.15 Simple Small Signal Model for Peak Current Mode Control
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Enable and Adjusting Undervoltage Lockout
      3. 8.1.3 Sequencing
      4. 8.1.4 Selecting the Switching Frequency
      5. 8.1.5 How to Interface to RT/CLK Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter for 3.3-V Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Selecting the Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection (LO)
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Catch Diode
          5. 8.2.1.2.5  Input Capacitor
          6. 8.2.1.2.6  Slow Start Capacitor
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  Undervoltage Lockout (UVLO) Set Point
          9. 8.2.1.2.9  Output Voltage and Feedback Resistors Selection
          10. 8.2.1.2.10 Compensation
          11. 8.2.1.2.11 Discontinuous Mode and Eco Mode Boundary
          12. 8.2.1.2.12 Power Dissipation Estimate
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Power Supply
      3. 8.2.3 Split Rail Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Estimated Circuit Area
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

5 Pin Configuration and Functions

DGQ Package
10-Pin VSSOP
Top View
TPS54060 po_DGQ_lvs919.gif
DRC Package
10-Pin VSON
Top View
TPS54060 po_DRC_lvs919.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 1 I A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the integrated gate driver for the high-side power MOSFET, the output is forced to switch off until the capacitor is refreshed.
COMP 8 I Error amplifier output and input to the output switch current comparator. Connect frequency compensation components to this pin.
EN 3 I Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input undervoltage lockout with resistor divider.
GND 9 – Ground
PH 10 O The source of the internal high-side power MOSFET.
Thermal pad 11 – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
PWRGD 6 O An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or EN shut down.
RT/CLK 5 I Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function.
SS/TR 4 I Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN 2 I Input supply voltage, 3.5 V to 60 V.
VSENSE 7 I Inverting node of the transconductance (gm) error amplifier.