ZHCSQP5 august   2023 TPS51386

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation and D-CAP3™ Control Mode
      2. 7.3.2  VCC LDO
      3. 7.3.3  Soft Start
      4. 7.3.4  Enable Control
      5. 7.3.5  Power Good
      6. 7.3.6  Overcurrent Protection and Undervoltage Protection
      7. 7.3.7  UVLO Protection
      8. 7.3.8  Overvoltage Protection
      9. 7.3.9  Output Voltage Discharge
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Out-of-Audio™ Mode
      3. 7.4.3 Power Save Mode (PSM)
  9. 8  Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor Selection
          3. 8.2.2.1.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-20230815-SS0I-ZV7H-ZPP2-VMXVQPQWZ4M8-low.svg Figure 5-1 RJN Package12-Pin VQFN-HRTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
VIN

1

 P Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and PGND.
PGND

2

 G Power ground terminal for the internal power FET.
PG

3

 O Open Drain Power-Good Indicator. This pin is asserted low if output voltage is out of PG threshold, overvoltage or if the device is under thermal shutdown, EN shutdown or during soft start.
FB

4

 I TPS51386 uses FB pin to regulate output voltage via feedback resistor divider network.
SS 5 O Soft-start time selection pin for TPS51386. Connecting an external capacitor sets the soft-start time and if no external capacitor is connected, the soft-start time is approximately 1 ms.
NC

6

 - No connect pin
SW

7

 O Switch node terminal. Connect the output inductor to this pin.

VBST

8

 I Supply input for the high-side MOSFET gate drive. Connect the bootstrap capacitor between VBST and SW.
VCC

9

 O 5-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass this pin with a 1-µF capacitor.
AGND

10

 G Ground of internal analog circuitry. Connect AGND to PGND at a single point close to AGND.
EN

11

 I Enable pin of buck converter. EN pin is a digital input pin, pull up to enable the converter, pull down to disable. Internal pulldown if EN pin is floating.

MODE

12

I

Mode selection pin. Connect MODE pin to VCC, or pull above 0.8 V for OOA mode operation, connect MODE to AGND or float for Power Save Mode. Internal pulldown if MODE pin is floating.