ZHCSDN8 March   2015 TPS51275B-1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 典型应用图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PWM Operations
      2. 8.3.2  Adaptive On-Time and PWM Frequency Control
      3. 8.3.3  Light-Load Condition in Out-of-Audio Operation
      4. 8.3.4  Enable and Power Good
      5. 8.3.5  Soft-Start and Discharge
      6. 8.3.6  VREG5 and VREG3 Linear Regulators
      7. 8.3.7  VCLK for Charge Pump
      8. 8.3.8  Overcurrent Protection
      9. 8.3.9  Output Overvoltage and Undervoltage Protection
      10. 8.3.10 Undervoltage Lockout Protection
      11. 8.3.11 Over-Temperature Protection (OTP)
    4. 8.4 Device Functional Modes
      1. 8.4.1 D-CAP Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Components Selection
          1. 9.2.2.1.1 Step 1. Determine the Value of R1 and R2
          2. 9.2.2.1.2 Step 2. Select the Inductor
          3. 9.2.2.1.3 Step 3. Select Output Capacitors
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Routing (Sensitive Analog Portion)
      3. 11.1.3 Routing (Power portion)
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage(2) VBST1, VBST2 –0.3 32 V
VBST1, VBST2(3) –0.3 6
SW1, SW2 –6.0 26
VIN –0.3 26
EN1, EN2 –0.3 6
VFB1, VFB2 –0.3 3.6
VO1 –0.3 6
Output voltage(2) DRVH1, DRVH2 –6.0 32 V
DRVH1, DRVH2(3) –0.3 6
DRVH1, DRVH2(3) (pulse width < 20 ns) –2.5 6
DRVL1, DRVL2 –0.3 6
DRVL1, DRVL2 (pulse width < 20 ns) –2.5 6
PGOOD, VCLK, VREG5 –0.3 6
VREG3, CS1, CS2 –0.3 3.6
Junction temperature, TJ 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted
(3) Voltage values are with respect to SW terminals.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage VIN 5 24 V
Input voltage(1) VBST1, VBST2 –0.1 30 V
VBST1, VBST2(2) –0.1 5.5
SW1, SW2 –5.5 24
EN1, EN2 –0.1 5.5
VFB1, VFB2 –0.1 3.5
VO1 –0.1 5.5
Output voltage(1) DRVH1, DRVH2 –5.5 30 V
DRVH1, DRVH2(2) –0.1 5.5
DRVL1, DRVL2 –0.1 5.5
PGOOD, VCLK, VREG5 –0.1 5.5
VREG3, CS1, CS2 –0.1 3.5
Operating free-air temperature, TA –40 85 °C
(1) All voltage values are with respect to the network ground terminal unless otherwise noted.
(2) Voltage values are with respect to the SW terminal.

7.4 Thermal Information

THERMAL METRIC(1) RUK (WQFN) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 94.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.1
RθJB Junction-to-board thermal resistance 64.3
ψJT Junction-to-top characterization parameter 31.8
ψJB Junction-to-board characterization parameter 58.0
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVIN1 VIN supply current-1 TA = 25°C, No load, VVO1 = 0 V 860 μA
IVIN2 VIN supply current-2 TA = 25°C, No load 30 μA
IVO1 VO1 supply current TA = 25°C, No load, VVFB1 = VVFB2 = 2.05 V 900 μA
IVIN(STBY) VIN stand-by current TA = 25°C, No load, VVO1 = 0 V, VEN1= VEN2 = 0 V 180 μA
INTERNAL REFERENCE
VFBx VFB regulation voltage TA = 25°C 1.99 2 2.01 V
1.98 2 2.02
VREG5 OUTPUT
VVREG5 VREG5 output voltage TA = 25°C, No load, VVO1 = 0 V 4.9 5 5.1 V
VVIN > 7 V , VVO1 = 0 V, IVREG5 < 100 mA 4.85 5 5.1
VVIN > 5.5 V , VVO1 = 0 V, IVREG5 < 35 mA 4.85 5 5.1
VVIN > 5 V, VVO1 = 0 V, IVREG5 < 20 mA 4.50 4.75 5.1
IVREG5 VREG5 current limit VVO1 = 0 V, VVREG5 = 4.5 V, VVIN = 7 V 100 150 mA
RV5SW 5-V switch resistance TA = 25°C, VVO1 = 5 V, IVREG5 = 50 mA 1.8 Ω
VREG3 OUTPUT
VVREG3 VREG3 output voltage No load, VVO1= 0 V, TA = 25°C 3.267 3.3 3.333 V
VVIN > 7 V , VVO1= 0 V, IVREG3< 100 mA 3.217 3.3 3.383
5.5 V < VVIN , VVO1= 0 V, IVREG3< 35 mA 3.234 3.3 3.366
0°C ≤ TA ≤ 85°C, VVIN > 5.5 V, VVO1 = 0 V,
IVREG3< 35 mA		 3.267 3.3 3.333
0°C ≤ TA ≤ 85°C, VVIN > 5.5 V, VVO1 = 5 V,
IVREG3 < 35 mA		 3.267 3.3 3.333
VVIN > 5 V, VVO1 = 0 V, IVREG3< 35 mA 3.217 3.3 3.366
IVREG3 VREG3 current limit VVO1 = 0 V, VVREG3 = 3.0 V, VVIN= 7 V 100 150 mA
MOSFET DRIVERS
RDRVH DRVH resistance Source, (VVBST – VDRVH) = 0.25 V, (VVBST – VSW) = 5 V 3 Ω
Sink, (VDRVH – VSW) = 0.25 V, (VVBST – VSW) = 5 V 1.9
RDRVL DRVL resistance Source, (VVREG5 – VDRVL) = 0.25 V, VVREG5 = 5 V 3 Ω
Sink, VDRVL = 0.25 V, VVREG5= 5 V 0.9
INTERNAL BOOT STRAP SWITCH
RVBST (ON) Boost switch on-resistance TA = 25°C, IVBST = 10 mA 13 Ω
IVBSTLK VBST leakage current TA = 25°C 1 µA
CLOCK OUTPUT
RVCLK (PU) VCLK on-resistance (pullup) TA = 25°C 10 Ω
RVCLK (PD) VCLK on-resistance (pulldown) TA = 25°C 10 Ω
OUTPUT DISCHARGE
RDIS1 CH1 discharge resistance TA = 25°C, VVO1 = 0.5 V
VEN1 = VEN2 = 0 V		 35 Ω
RDIS2 CH2 discharge resistance TA = 25°C, VSW2 = 0.5 V, VEN1 = VEN2 = 0 V 70 Ω
POWER GOOD
VPGTH PG threshold Lower (rising edge of PG-in) 92.5% 95.0% 97.5%
Hysteresis 5%
Upper (rising edge of PG-out) 107.5% 110.0% 112.5%
Hysteresis 5%
IPGMAX PG sink current VPGOOD = 0.5 V 6.5 mA
IPGLK PG leakage current VPGOOD = 5.5 V 1 µA
CURRENT SENSING
ICS CS source current TA = 25°C, VCS= 0.4 V 9 10 11 μA
TCCS CS current temperature coefficient(1) On the basis of 25°C 4500 ppm/°C
VCS CS current-limit setting range 0.2 2 V
VZC Zero cross detection offset TA = 25°C –1 1 3 mV
LOGIC THRESHOLD
VENX(ON) EN threshold high-level SMPS on level 1.6 V
VENX(OFF) EN threshold low-level SMPS off level 0.3 V
IEN EN input current VENx= 3.3 V –1 1 µA
OUTPUT OVERVOLTAGE PROTECTION
VOVP OVP trip threshold 112.5% 115.0% 117.5%
OUTPUT UNDERVOLTAGE PROTECTION
VUVP UVP trip threshold 55% 60% 65%
UVLO
VUVL0VIN VIN UVLO threshold Wake up 4.58 V
Hysteresis 0.5
VUVLO5 VREG5 UVLO threshold Wake up 4.38 4.5 V
Hysteresis 0.4
VUVLO3 VREG3 UVLO threshold Wake up 3.15 V
Hysteresis 0.15
OVERTEMPERATURE PROTECTION
TOTP OTP threshold(1) Shutdown temperature 155 °C
Hysteresis 10
(1) Ensured by design. Not production tested.

7.6 Timing Requirements

over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V (unless otherwise noted)
MIN NOM MAX UNIT
DUTY CYCLE AND FREQUENCY CONTROL
fsw1 CH1 frequency(1) TA = 25°C, VVIN= 20 V 240 300 360 kHz
fSW2 CH2 frequency(1) TA = 25°C, VVIN= 20 V 280 355 430 kHz
tOFF(MIN) Minimum off-time TA = 25°C 200 300 500 ns
MOSFET DRIVERS
tD Dead time DRVH-off to DRVL-on 12 ns
DRVL-off to DRVH-on 20

7.7 Switching Characteristics

over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLOCK OUTPUT
fCLK Clock frequency TA = 25°C 260 kHz
SOFT-START OPERATION
tSS Soft-start time From ENx = HI and VVREG5 > VUVLO5 to VOUT = 95% 3.25 ms
tSSRAMP Soft-start time (ramp-up) VOUT= 0% to VOUT = 95%, VVREG5 = 5 V 3.12 ms
POWER GOOD
tPGDEL PG delay From PG lower threshold (95% = typical) to PG flag high 1.38 ms
OUTPUT OVERVOLTAGE PROTECTION
tOVPDLY OVP propagation delay TA = 25°C 0.5 µs
OUTPUT UNDERVOLTAGE PROTECTION
tUVPDLY UVP propagation delay 250 µs
tUVPENDLY UVP enable delay From ENx = HI and VVREG5 > VUVLO5 to UV latch off 4.3 ms

7.8 Typical Characteristics

TPS51275B-1 temp_char_001.png
Figure 1. VIN Supply Current 1 vs Junction Temperature
TPS51275B-1 temp_char_003.png
Figure 3. VO1 Supply Current 1 vs Junction Temperature
TPS51275B-1 temp_char_005.png
Figure 5. CS Source Current vs Junction Temperature
TPS51275B-1 D001_slvsct3.gif
Out-of-Audio mode VVOUT1 = 5 V
Figure 7. Efficiency vs Output Current
TPS51275B-1 D002_slvsct3.gif
Out-of-Audio mode VVOUT2 = 3.3 V
Figure 9. Efficiency vs Output Current
TPS51275B-1 D005_slvsct3.gif
Out-of-Audio mode VVOUT1 = 5 V
Figure 11. Switching Frequency vs Output Current
TPS51275B-1 vin_5_fsw_slvsct3.gif
VOUT1 = 5 V IOUT1 = 6 A
Figure 13. Switching Frequency vs Input Voltage
TPS51275B-1 temp_char_002.png
Figure 2. VIN Supply Current 2 vs Junction Temperature
TPS51275B-1 temp_char_004_slvsct3.gif
Figure 4. VIN Stand-By Current vs Junction Temperature
TPS51275B-1 temp_char_006.png
Figure 6. Clock Frequency vs Junction Temperature
TPS51275B-1 D003_slvsct3.gif
Out-of-Audio mode VVOUT1 = 5 V
Figure 8. Load Regulation
TPS51275B-1 D004_slvsct3.gif
Out-of-Audio mode VVOUT2 = 3.3 V
Figure 10. Load Regulation
TPS51275B-1 D006_slvsct3.gif
Out-of-Audio mode VVOUT2 = 3.3 V
Figure 12. Switching Frequency vs Output Current
TPS51275B-1 vin_33_fsw_slvsct3.gif
VOUT2 = 3.3 V IOUT2 = 6 A
Figure 14. Switching Frequency vs Input Voltage