ZHCSM82A April   2022  – September 2023 TPS38

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1.     8
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
      7. 8.3.7 Adjustable Voltage Thresholds
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Voltage – Fast AC Signal Monitoring For Power Fault Detection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Dissipation and Device Operation
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Creepage Distance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表

封装选项

机械数据 (封装 | 引脚)
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订购信息

9.2.1.1 Design Requirements

This design requires voltage supervision on an AC, with a known operating frequency, power supply rail. The undervoltage fault sensing is achieved by monitoring the DC output of a full bridge rectifier while the undervoltage fault is detected by inputting a half wave signal and its voltage frequency and magnitude are being monitored. The target output of this TPS38 application is for 5V reset logic.

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PARAMETER DESIGN REQUIREMENT DESIGN RESULT
Power rail voltage Supervision Monitor 24 VAC 800 Hz power supply for undervoltage conditions. Trigger undervoltage fault at 5 V and at 25.5 V. TPS38 provides voltage monitoring with 1.5% max accuracy with adjustable/non-adjustable variations.
Maximum input voltage Operate with power supply input up to 34 V. The TPS38 can support a VDD of up to 65 V.
Output logic voltage Open-Drain Output Topology An open-drain output is recommended to provide the a 5 V reset signal.
SENSE1 delay when a fault is detected RESET1 delay of at least 1.28 ms CCTS1 = 10 nF sets 1.28 ms delay
SENSE2 delay when a fault is detected RESET2 delay of at least 0.625 ms which is the time between half wave cycles CCTS2 = 5.6 nF sets 717 µs delay
RESET1 delay when returning from a fault RESET1 delay of at least 12.8 ms CCTR1 = 10 nF sets 12.8 ms delay
Voltage monitor accuracy Maximum voltage monitor accuracy of 1.5%. The TPS38 has 1.5% maximum voltage monitor accuracy.