ZHCSMU7E august   2020  – august 2023 TPS38-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
      7. 8.3.7 Adjustable Voltage Thresholds
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Adjustable Voltage Thresholds
    2. 9.2 Application Information
    3. 9.3 Typical Application
      1. 9.3.1 Design 1: Automotive Off-Battery Monitoring
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Detailed Design Procedure
        3. 9.3.1.3 Application Curves
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Dissipation and Device Operation
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Creepage Distance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表

封装选项

机械数据 (封装 | 引脚)
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订购信息

7.7 Timing Diagrams

GUID-20230727-SS0I-VKRD-60GF-GMKZWLZBKBNV-low.svgFigure 7-1 Voltage Threshold and Hysteresis Accuracy
GUID-20210530-CA0I-L6MQ-KVNH-PKQQ6VCQL7HM-low.svg
A. For open-drain output option, the timing diagram assumes the RESETx_UVOD / RESETx_UVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 7-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time.
C. RESETx_UVxx / RESETx_UVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached.
Figure 7-2 SENSEx Undervoltage (UV) Timing Diagram
GUID-20210530-CA0I-GC7B-ZXZM-ZXQSXFVV33HV-low.svg
A. For open-drain output option, the timing diagram assumes the RESETx_OVOD / RESETx_OVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 7-3 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time.
C. RESETx_OVxx / RESETx_OVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached.
Figure 7-3 SENSEx Overvoltage (OV) Timing Diagram