SNVSCF8A June   2023  – October 2026 TPS3436

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Window Watchdog Timer
        1. 7.3.1.1 tWC (Close Window) Timer
        2. 7.3.1.2 tWO (Open Window) Timer
        3. 7.3.1.3 Watchdog Enable Disable Operation
        4. 7.3.1.4 tSD Watchdog Start Up Delay
        5. 7.3.1.5 SET Pin Behavior
      2. 7.3.2 Manual RESET
      3. 7.3.3 WDO Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Assert Delay
        1. 8.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Watchdog Window Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a Microcontroller Watchdog During Operational and Sleep Modes
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Determining Window Timings During Operation and Sleep Modes
          2. 8.2.1.2.2 Meeting the Output Assert Delay
          3. 8.2.1.2.3 Setting the Watchdog Window
          4. 8.2.1.2.4 Calculating the WDO Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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8.4.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected.

  • Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1µF ceramic capacitor as near as possible to the VDD pin.
  • Place CCRST capacitor as close as possible to the CRST pin.
  • Place CCWD capacitor as close as possible to the CWD pin.
  • Place the pullup resistor on the WDO pin as close to the pin as possible.