SLVSBE9E April   2012  – June 2015 TPS27081A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 PFET Q1 Minimum Safe Operating Area (SOA)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 ON/OFF
      2. 7.4.2 Fastest Output Rise Time
      3. 7.4.3 Controlled Output Rise Time
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Standard Load Switching Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Configuring Q1 ON Resistance
          2. 8.2.1.2.2 Configuring Turnon Slew Rate
          3. 8.2.1.2.3 Configuring Turnoff Delay
          4. 8.2.1.2.4 Low Voltage ON/OFF Interface
          5. 8.2.1.2.5 ON-Chip Power Dissipation
        3. 8.2.1.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Standby Power Isolation
      2. 8.3.2 Boost Regulator With True Shutdown
      3. 8.3.3 Single Module Multiple Power Supply Sequencing
      4. 8.3.4 Multiple Modules Interdependent Power Supply Sequencing
      5. 8.3.5 TFT LCD Module Inrush Current Control
      6. 8.3.6 Multiple Modules Interdependent Supply Sequencing Without a GPIO Input
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Reliability
    4. 10.4 Improving Package Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

5 Pin Configuration and Functions

DDC Package
6-Pin SOT
Top View
TPS27081A ddc6_sot_pinout_slvsbe9.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
ON/OFF 5 I Active high enable. When driven with a high-impedance driver, connect an external pull down resistor to GND
R1/C1 6 I Gate terminal of power PFET (Q1)
R2 1 O Source terminal of NMOS (Q2) . Connect to system GND directly or through a slew rate control resistor
VIN 4 I Source terminal of power PFET (Q1). Connect a pull-up resistor between the pins VIN/R1 and R1/C1
VOUT 2 O Drain terminal of power PFET (Q1). Connect a slew control capacitor between pins VOUT and R1/C1
3
(1) I = Input, O = Output