ZHCS791C March   2012  – July 2015 TPS2378

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD Auxiliary Power Detect
      2. 7.3.2  CDB Converter Disable Bar Pin Interface
      3. 7.3.3  CLS Classification
      4. 7.3.4  DEN Detection and Enable
      5. 7.3.5  Internal Pass MOSFET
      6. 7.3.6  T2P Type-2 PSE Indicator
      7. 7.3.7  VDD Supply Voltage
      8. 7.3.8  VSS
      9. 7.3.9  PowerPAD
      10. 7.3.10 Forced, Four-Pair, High Power PoE
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Start-up Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Inrush and Start-up
      7. 7.4.7  Maintain Power Signature
      8. 7.4.8  Start-up and Converter Operation
      9. 7.4.9  PD Hotswap Operation
      10. 7.4.10 Start-up and Power Management, CDB and T2P
      11. 7.4.11 Adapter ORing
      12. 7.4.12 Using DEN to Disable PoE
      13. 7.4.13 ORing Challenges
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1 Input Bridges and Schottky Diodes
        2. 8.2.2.2 Protection, D1
        3. 8.2.2.3 Capacitor, C1
        4. 8.2.2.4 Detection Resistor, RDEN
        5. 8.2.2.5 Classification Resistor, RCLS
        6. 8.2.2.6 APD Pin Divider Network RAPD1, RAPD2
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档 
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

The layout of the PoE front end should follow power and EMI/ESD best practice guidelines. A basic set of recommendations include:

  • Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode bridges, TVS and 0.1-μF capacitor, and TPS2378.
  • All leads should be as short as possible with wide power traces and paired signal and return.
  • There should not be any crossovers of signals from one part of the flow to another.
  • Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage rails and between the input and an isolated converter output.
  • The TPS2378 should be located over split, local ground planes referenced to VSS for the PoE input and to RTN for the switched output.
  • Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or overlay copper fills should be used in the power path.

Layout Example

Figure 27 and Figure 28 show the top and bottom layer and assemblies of the TPS2378EVM-105 as a reference for optimum parts placement. A detailed PCB layout can be found in the user’s guide of the TPS2378EVM-105 (SLVU682).

TPS2378 top_side_slvsb99.png Figure 27. Top Side
TPS2378 bottom_side_slvsb99.png Figure 28. Bottom Side

EMI Containment

  • Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).
  • Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes (minimize exposed radiating surface).
  • Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with ground floods).
  • Use 4 layer PCB if economically feasible (for better grounding).
  • Minimize the amount of copper area associated with input traces (to minimize radiated pickup).
  • Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane.
  • Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth ground).
  • Use of ferrite beads on input (allow for possible use of beads or 0 ohm resistors).
  • Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as boundary line).
  • Possible use of common-mode inductors.
  • Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations).
  • End-product enclosure considerations (shielding).

Thermal Considerations and OTSD

Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations assume that the TPS2378 is the only heat source contributing to the PCB temperature rise. It is possible for a normally operating TPS2378 device to experience an OTSD event if it is excessively heated by a nearby device.

ESD

ESD requirements for a unit that incorporates the TPS2378 have a much broader scope and operational implications than are used in TI’s testing. Unit-level requirements should not be confused with reference design testing that only validates the ruggedness of the TPS2378.