10.1.1 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a discharged load capacitor or short-circuit, a capacitor needs to be placed between V_IN and GND. A 1-µF ceramic capacitor, C_IN, placed close to the pins, is usually sufficient. Higher values of C_IN can be used to further reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. For the fastest slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to avoid excessive voltage drop.

10.1.2 Output Capacitor (Optional)

Due to the integrated body diode of the NMOS switch, a C_IN greater than C_L is highly recommended. A C_L greater than C_IN can cause V_OUT to exceed V_IN when the system supply is removed. This could result in current flow through the body diode from V_OUT to V_IN. A C_IN to C_L ratio of at least 10 to 1 is recommended for minimizing V_IN dip caused by inrush currents during startup. For the fastest slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to minimize V_IN dip caused by inrush currents during startup.

10.1.3 Switch from GPIO Control to I²C Control (and vice versa)

The TPS22994 can be switched from GPIO control to I²C (and vice versa) mode by writing to the control register of the device. Each device has a single control register and is located at register address 05h. The register’s composition is as follows:

The higher four bits of the control register dictates if the device is in GPIO control (bit set to ‘0’) or I²C control (bit set to ‘1’). The transition from GPIO control to I²C control can be made with a single write command to the control register. See Figure 44 for the composition of a single write command. It is recommended that the channel of interest is transitioned from GPIO control to I²C control with the first write command and followed by a second write command to enable the channel via I²C control. This will ensure a smooth transition from GPIO control to I²C control.

10.1.4 Configuration of Configuration Registers

The TPS22994 contains four configuration registers (one for each channel) and are located at register addresses 01h through 04h. The register’s composition is as follows (single channel shown for clarity):

10.1.5 Configuration of Mode Registers

The TPS22994 contains twelve mode registers located at register addresses 06h through 11h. These mode registers allow the user to turn-on or turn-off multiple channels in a single TPS22994 or multiple channels spanning multiple TPS22994 devices with a single SwitchALL^TM command.

For example, an application may have multiple power states (e.g. sleep, active, idle, etc.) as shown in Figure 51.

Figure 51. Application Example of Power States

In each of the different power states, different combinations of channels may be on or off. Each power state may be associated with a single mode register (Mode1, Mode2, etc.) across multiple TPS22994 as shown in Table 2. For example, with 7 quad-channel devices, up to 28 rails can be enabled/disabled with a single SwitchALL^TM command.

The contents of the lower four bits of the mode register is copied into the lower four bits of the control register during an SwitchALL^TM command. The address of the mode register to be copied is specified in the SwitchALL^TM command (see Figure 48 for the structure of the SwitchALL^TM command). By executing a SwitchALL^TM command, the application will apply the different on/off combinations for the various power states with a single command rather than having to turn on/off each channel individually by re-configuring the control register. This reduces the latency and allows the application to control multiple channels synchronously. The example above shows the application using three mode registers, but the TPS22994 contains twelve mode registers, allowing for up to twelve power states.

The mode register’s composition is as follows (single mode register shown for clarity):

The lower four bits of the mode registers are copied into the lower four bits of the control register during an all-call command.

10.1.6 Turn-on/Turn-off of Channels

By default upon power up VBIAS, all the channels of the TPS22994 are controlled via the ONx pins. Using the I²C interface, each channel be controlled via I²C control as well. The channels of the TPS22994 can also be switched on or off by writing to the control register of the device. Each device has a single control register and is located at register address 05h. The register’s composition is as follows:

The lower four bits of the control register dictate if the channels of the device are off (bit set to ‘0’) or on (bit set to ‘1’) during I²C control. The transition from off to on can be made with a single write command to the control register. See Figure 44 for the composition of a single write command.

10.2.1 Tying Multiple Channels in Parallel

Two or more channels of the device can be tied in parallel for applications that require lower R_ON and/or more continous current. Tying two channels in parallel will result in half of the R_ON and two times the I_MAX capability. Tying three channels in parallel will result in one-third of the R_ON and three times the I_MAX capability. Tying four channels in parallel will result in one-fourth of the R_ON and four times the I_MAX capability. For the channels that are tied in parallel, it is recommended that the ONx pins be tied together for synchronous control of the channels when in GPIO control. In I²C control, all four channels can be enabaled or disabled synchronously by writing to the control register of the device. Figure 54 shows an application example of tying all four channels in parallel.

Figure 54. Parallel Channels

10.2.2 Cold Boot Programming of All Registers

Since the TPS22994 has a digital core with volatile memory, upon power cycle of the VBIAS pin, the registers will revert back to their default values (see register map for default values). Therefore, the application must reprogram the configuration registers, control register, and mode registers if non-default values are desired. The TPS22994 contains 17 programmable registers (4 configuration registers, 1 control register, 12 mode registers) in total.

During cold boot when the microcontroller and the I²C bus is not yet up and running, the channels of the TPS22994 can still be enabled via GPIO control. One method to achieve this is to tie the ONx pin to the respective VINx pin for the channels that need to turn on by default during cold boot. With this method, when VINx is applied to the TPS22994, the channel will be enabled as well. Once the I²C bus is active, the channel can be switched over to I²C control to be disabled. See Figure 55 for an example of how the ONx pins can be tied to VINx for default enable during cold boot.

Figure 55. Cold Boot Programming

10.2.3 Power Sequencing Without I²C

It is also possible to power sequence the channels of the device during a cold boot when there is no I²C bus present for control. One method to accomplish this it to tie the VOUT of one channel to the ON pin of the next channel in the sequence. For example, if the desired power up sequence is VOUT3, VOUT1, VOUT2, and VOUT4 (in that order), then the device can be configured for GPIO control as shown in Figure 56. The device will power up with default slew rate, ON-delay, and QOD values as specified in the register map.

Figure 56. Power Sequencing Without I²C Schematic

10.2.3.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

• V_INx voltage
• Load Current

10.2.3.2.1 VIN to VOUT Voltage Drop

The VINx to VOUTx voltage drop in the device is determined by the R_ON of the device and the load current. The R_ON of the device depends upon the VIN conditions of the device. Refer to the R_ON specification of the device in the Electrical Characteristics table of this datasheet. Once the R_ON of the device is determined based upon the VINx conditions, use Equation 2 to calculate the VINx to VOUTx voltage drop:

Equation 2. ∆V = I_LOAD × R_ON

Where:

ΔV = voltage drop from VINx to VOUTx
I_LOAD = load current
R_ON = On-resistance of the device for a specific V_IN

An appropriate I_LOAD must be chosen such that the I_MAX specification of the device is not violated.

10.2.3.2.2 Inrush Current

To determine how much inrush current will be caused by the C_L capacitor, use Equation 3:

Equation 3.

Where:

I_INRUSH = amount of inrush caused by C_L
C_L = capacitance on VOUTx
dt = rise time in VOUT during the ramp up of VOUTx when the device is enabled
dV_OUT = change in VOUT during the ramp up of VOUTx when the device is enabled

An appropriate C_L value should be placed on VOUTx such that the I_MAX specifications of the device are not violated.

10.2.3.3 Application Curves

VBIAS = 7.2V	VINx = 3.6V	VDD = 3.6V
RL = 10Ω	TA = 25°C

Figure 57. +Power Up With Different Slew Rate Settings

VBIAS = 7.2V	VINx = 3.6V	VDD = 3.6V
RL = 10Ω	TA = 25°C

Figure 58. Power Up With Different tD Settings

VBIAS = 7.2V	VINx = 3.6V	VDD = 3.6V
RL = 10Ω	TA = 25°C

Figure 59. Power Down With Different QOD Settings With R_L = 10 Ω

VBIAS = 7.2V	VINx = 3.6V	VDD = 3.6V
RL = 10Ω	TA = 25°C

Figure 61. I2C Read Sequence

VBIAS = 7.2V	VINx = 3.6V	VDD = 3.6V
RL = 10Ω	TA = 25°C

Figure 63. Enabling Channel 1 Across Two TPS22994 Devices With the SwitchALL^TM Command

A.

VBIAS = 7.2V	VINx = 3.6V	VDD = 3.6V
RL = Open	TA = 25°C

Figure 60. Power Down With Different QOD Settings With R_L = Open

VBIAS = 7.2V	VINx = 3.6V	VDD = 3.6V
RL = 10Ω	TA = 25°C
This example shows the channel of the device being turned on when a I2C "enable" command is written to the register.

Figure 62. I2C Write Sequence