ZHCSC50B February   2014  – September 2014 TPS22961

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics, VBIAS = 5.0 V
    6. 7.6 Electrical Characteristics, VBIAS = 3.0 V
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 On/off Control
      2. 8.3.2 Input Capacitor (CIN)
      3. 8.3.3 Output Capacitor (CL)
      4. 8.3.4 VIN and VBIAS Voltage Range
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application Powering a Downstream Module
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VIN to VOUT Voltage Drop
          2. 9.2.1.2.2 Inrush Current
          3. 9.2.1.2.3 Thermal Considerations
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application Powering Rails Sensitive to Ringing and Overvoltage due to Fast Rise Time
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Picking Proper Inductor and Capacitor to Meet Voltage Overshoot Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 商标
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13机械封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DNY|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

This section will highlight some of the design considerations when implementing this device in various applications. A PSPICE model for this device is also available in the product page of this device on www.ti.com for further aid.

9.2 Typical Application

9.2.1 Typical Application Powering a Downstream Module

This application demonstrates how the TPS22961 can be used to power downstream modules.

TPS22961 app1_detail_slvsci4.gif Figure 26. Typical Application Schematic for Powering a Downstream Module

9.2.1.1 Design Requirements

For this design example, use the following as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VIN 1.05 V
VBIAS 5.0 V
Load current 6 A

9.2.1.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

  • VIN voltage
  • VBIAS voltage
  • Load current

9.2.1.2.1 VIN to VOUT Voltage Drop

The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The RON of the device depends upon the VIN and VBIAS conditions of the device. Refer to the RON specification of the device in the Electrical Characteristics table of this datasheet. Once the RON of the device is determined based upon the VIN and VBIAS conditions, use Equation 1 to calculate the VIN to VOUT voltage drop:

Equation 1. TPS22961 eq1_delta_slvsci4.gif

where

  • ΔV = voltage drop from VIN to VOUT
  • ILOAD = load current
  • RON = On-resistance of the device for a specific VIN and VBIAS combination

An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.

9.2.1.2.2 Inrush Current

To determine how much inrush current will be caused by the CL capacitor, use Equation 2:

Equation 2. TPS22961 Eq2_Iinrush_slvsci4.gif

where

  • IINRUSH = amount of inrush caused by CL
  • CL = capacitance on VOUT
  • dt = time it takes for change in VOUT during the ramp up of VOUT when the device is enabled
  • dVOUT = change in VOUT during the ramp up of VOUT when the device is enabled

An appropriate CL value should be placed on VOUT such that the IMAX and IPLS specficiations of the device are not violated.

9.2.1.2.3 Thermal Considerations

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 3.

Equation 3. TPS22961 eq_thrm_slvsci4.gif

where

  • PD(max) = maximum allowable power dissipation
  • TJ(max) = maximum allowable junction temperature (125°C for the TPS22961)
  • TA = ambient temperature of the device
  • ΘJA = junction to air thermal impedance. See Thermal Information section. This parameter is highly dependent upon board layout.

9.2.1.3 Application Curves

TPS22961 C031_slvsci7.png
VBIAS = 5 V VIN = 2.5 V CIN = 1 µF
CL = 0.1 µF
Figure 27. tR at VBIAS = 5 V
TPS22961 C032_slvsci7.png
VBIAS = 5 V VIN = 1.05 V CIN = 1 µF
CL = 0.1 µF
Figure 29. tR at VBIAS = 3 V
TPS22961 C033_slvsci7.png
VBIAS = 5 V VIN = 0.8 V CIN = 1 µF
CL = 0.1 µF
Figure 28. tR at VBIAS = 5 V
TPS22961 C034_slvsci7.png
VBIAS = 5 V VIN = 0.8 V CIN = 1 µF
CL = 0.1 µF
Figure 30. tR at VBIAS = 3 V

9.2.2 Typical Application Powering Rails Sensitive to Ringing and Overvoltage due to Fast Rise Time

This application demonstrates how the TPS22961 can be used to power rails senstive to ringing and overvoltage that can often happen due to fast rise times.

TPS22961 app2_detail_slvsci4.gif Figure 31. Typical Application Schematic for Powering Rails Sensitive to Ringing

9.2.2.1 Design Requirements

For this design example, use the following as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VIN 1.05 V
VBIAS 5.0 V
Acceptable percent overshoot (ρ) 3.2%
Maximum settling time (tSETTLE) 40 µs

9.2.2.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

  • VIN voltage
  • VBIAS voltage
  • Acceptable percent overshoot
  • Maximum allowed settling time for the power rail

9.2.2.2.1 Picking Proper Inductor and Capacitor to Meet Voltage Overshoot Requirements

To determine the value of L and CL in the circuit, the damping factor associated with the acceptable percent overshoot must be calculated. To calculate the damping factor (ε), use Equation 4.

Equation 4. TPS22961 cap_eq1_slvsci4.gif

where

  • ε = damping factor of the LC filter
  • ρ = allowable percent overshoot for the power rail

Use the damping factor calculated in Equation 4 to determine the inductance (L), the DCR of the inductor (RDCR), and capacitance (CL) to achieve the percent overshoot. This will be an iterative process to determine the optimal combination of L and CL with standard value components available. Use Equation 5 to determine the combination of L, RDCR, and CL that is needed to satisfy damping factor calculated from Equation 4.

Equation 5. TPS22961 cap_eq2_slvsci4.gif

where

  • ε = damping factor of the LC filter
  • RDCR = DCR of the inductor
  • CL = the capacitance of the filter
  • L = the inductor of the filter

To determine the setting time (within 5% of steady state value) of the filter, use Equation 6.

Equation 6. TPS22961 eq_settle_slvsci4.gif

where

  • tSETTLE = settling time of filter to within 5% of steady state value
  • ε = damping factor of the LC filter
  • CL = the capacitance of the filter
  • L = the inductor of the filter

The combination of damping factor (ε) and filter settling time (tSETTLE) will bound the values for L, RDCR, and CL that can be used to meet the design constraints in Table 2.

Application Curves

TPS22961 C030_slvsci7.png Figure 32. Filtered Output (CH1 = VIN, CH2 = ON, CH3 = Output of LC filter, CH4 = VOUT of TPS22961)