ZHCSEX3A February 2016 – March 2016 TPS22918
PRODUCTION DATA.
11 Layout
11.1 Layout Guidelines
VIN and VOUT traces should be as short and wide as possible to accommodate for high current.
The VIN pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
11.2 Layout Example
Figure 32. Recommended Board Layout
11.3 Thermal Considerations
For best performance, all traces should be as short as possible. To be most effective, the input and output capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have on normal and short-circuit operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects along with minimizing the case to ambient thermal impedance.
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 14:
where
- PD(MAX) = maximum allowable power dissipation
- TJ(MAX) = maximum allowable junction temperature (125°C for the TPS22918)
- TA = ambient temperature of the device
- θJA = junction to air thermal impedance. Refer to the Thermal Information table. This parameter is highly dependent upon board layout.