12.1 Layout Guidelines

• Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low-inductance trace.
• When large transient currents are expected on the output, TI recommends placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin.
• The PowerPAD should be directly connected to PCB ground plane using wide and short copper trace.

12.2 Layout Example

Figure 34. Layout Recommendation

12.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS20xxC and TPS20xxC-2 dual. The system designer can control choices of package, proximity to other power dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors such as airflow and maximum ambient temperature are often determined by system considerations.

Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical.

The following procedure requires iteration because power loss is due to the two internal MOSFETs 2 × I² × r_DS(on), and r_DS(on) is a function of the junction temperature. As an initial estimate, use the r_DS(on) at 125°C from the typical characteristics, and the preferred package thermal resistance for the preferred board construction from the thermal parameters section.

If the calculated T_J is substantially different from the original assumption, look up a new value of r_DS(on) and recalculate.

If the resulting T_J is not less than 125°C, try a PCB construction and/or package with lower θ_JA.