TPD4E001-Q1 器件是一款低电容 TVS 二极管阵列,设计用于为通信线路中连接的敏感电子元件提供 ESD 保护。每个通道包含一对将 ESD 脉冲引导至 VCC 或者 GND 的瞬态电压抑制二极管。根据 IEC 61000-4-2 国际标准规定,TPD4E001-Q1 可防止接触放电电压高达 ±8kV 和气隙放电高达电压 ±15kV 的 ESD 事件发生。该器件每通道的电容低至 1.5pF,因此非常适用于高速数据接口。低泄露电流(最大 10nA)确保了系统的最低功耗和模块接口的高精度。
此外,此器件还适用于为使用 USB 2.0、以太网或高精度模拟接口的汽车音响主机、后座娱乐系统以及后座摄像机系统提供保护。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
TPD4E001-Q1 | SOT-23 (6) | 2.90mm x 1.60mm |
Changes from E Revision (June 2017) to F Revision
Changes from D Revision (March 2015) to E Revision
Changes from C Revision (June 2013) to D Revision
Changes from B Revision (February 2012) to C Revision
Changes from A Revision (April 2013) to B Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 2 | GND | Ground |
IO1 | 1 | I/O | ESD-protected channel |
IO2 | 3 | ||
IO3 | 4 | ||
IO4 | 6 | ||
VCC | 5 | I | Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.3 | 7 | V | |
VIO | I/O voltage tolerance | –0.3 | VCC + 0.3 | V | |
IPP | Peak pulse current (Tp = 8/20 µs)(2) | 5.5 | A | ||
PPP | Peak pulse power (Tp = 8/20 µs)(2) | 100 | W | ||
TA | Free air operating temperature | –40 | 125 | °C | |
TJ | Junction temperature | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±15000 | V | |
Charged-device model (CDM), per AEC Q100-011 | ±750 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | IEC 61000-4-2 contact discharge | ±8000 | V |
IEC 61000-4-2 air-gap discharge | ±15000 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | ISO 10605 (330 pF, 330 Ω) contact discharge | ±8000 | V |
ISO 10605 (330 pF, 330 Ω) air-gap discharge | ±15000 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
TA | Free air operating temperature | –40 | 125 | °C |
VCC pin | Operating voltage | 0.9 | 5.5 | V |
IO1, IO2, IO3, IO4 pins | Operating voltage | 0 | VCC | V |
THERMAL METRIC(1) | TPD4E001-Q1 | UNIT | |
---|---|---|---|
DBV (SOT-23) | |||
6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 202.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 146.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 47.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 37.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 46.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ICC | Supply current | 1 | 200 | nA | |||
VF | Diode forward voltage | IF = 10 mA | 0.65 | 0.95 | V | ||
VBR | Breakdown voltage | IBR = 10 mA | 11 | V | |||
VCLAMP | Clamping voltage | Surge strike(2) on IO pin, GND pin grounded, VCC = 5.5 V, IPP = 5.5 A | Positive transients | 16 | V | ||
VRWM | Reverse standoff voltage | IO pin to GND pin | 5.5 | V | |||
IIO | Channel leakage current | VIO = GND to VCC | ±10 | nA | |||
CIO | Channel input capacitance | VCC = 5 V, bias of VCC/2, f = 10 MHz | 1.5 | pF |
The TPD4E001-Q1 device is a low-capacitance, TVS diode array designed for ESD protection in sensitive electronics connected to communication lines. Each channel consists of a pair of transient voltage suppression diodes that steer ESD pulses to VCC or GND. The TPD4E001-Q1 device protects against ESD events up to ±8-kV contact discharge and ±15-kV air-gap discharge, as specified in IEC 61000-4-2 international standard. This device has a low capacitance of 1.5-pF per channel making it ideal for use in high-speed data interfaces. The low-leakage current (10 nA maximum) ensures minimum power consumption for the system and high accuracy for analog interfaces.
This device is qualified according to the AEC-Q100 standard. The device temperature rating is Grade 1 (–40°C to +125°C). The HBM Classification Level passed is 3B (> 8 kV). The CDM Classification Level passed is C5 (all pins 750 V to <1000 V).
The device is specified at ±8-kV contact discharge and ±15-kV air gap discharge.
This device is rated to pass at least 5.5-A of peak pulse current according to the IEC 61000-4-5 (8/20-µs pulse) standard.
This device has a typical capacitance of 1.5-pF on each of the four IO pins. This allows for high speed signals on the IO pins in excess of 1 Gbps.
This device is rated to have a maximum leakage current of 10-nA on each of the four IO pins.
This device is specified to operate with a supply voltage (on VCC) between 0.9-V and 5.5-V to ensure sufficient signal integrity.
The TPD4E001-Q1 device is a passive integrated circuit that triggers when voltages are above VBR or below the lower diodes VF (–0.6 V). During ESD events, voltages as high as ±8 kV (contact) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD4E001-Q1 (usually within 10s of nano-seconds) the device reverts back to its high-impedance state.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPD4E001-Q1 device is a TVS diode array which is typically used to provide a path to ground for dissipating ESD events on high-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
For this design example, one TPD4E001-Q1 device is being used in a dual USB 2.0 application. This provides a complete port protection scheme.
For this design example, a single TPD4E001-Q1 device is used to protect all the pins on two USB2.0 connectors.
Given the USB application, known parameters are listed in the Table 1.
DESIGN PARAMETER | VALUE |
---|---|
Signal range on IO1, IO2, IO3, or IO4 | 0 V to 3.6 V |
Voltage range on VCC | 0 V to 5.25 V |
Operating Frequency on IO1, IO2, IO3, or IO4 | 240 MHz |
To begin the design process, some parameters must be decided upon; the designer needs to know the following:
The TPD4E001-Q1 device has 4 identical protection channels for signal lines. The symmetry of the device provides flexibility when selecting which of the 4 IO channels protects which signal lines. Any IO supports a signal range of 0 to (VCC + 0.3) V. Therefore, this device supports the USB 2.0 signal swing assuming VCC is set appropriately.
The VCC pin can be connected in one of two ways:
If this pin is connected to the USB 2.0 VBUS supply or left floating, the allowable signal swing is enough for a USB 2.0 application.
Each IO pin on the TPD4E001-Q1 device has a typical capacitance of 1.5 pF. This capacitance is low enough to easily support USB 2.0 data rates.
This device is a passive ESD protection device so there is no need to power it. Do not violate the maximum voltage specifications for each pin.
When placed near the connector, the TPD4E001-Q1 device's ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage-current specifications. The TPD4E001-Q1 device ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, observe the following layout and design guidelines:
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这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损伤。
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