ZHCSD89A October   2014  – January 2015 TPD3S014 , TPD3S044

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 简化电路原理图
  5. 修订历史记录
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics: TJ = TA = 25°C
    6. 8.6 Electrical Characteristics: -40°C ≤ TJ ≤ 125°C
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Lockout (UVLO)
      2. 9.3.2 Enable
      3. 9.3.3 Internal Charge Pump
      4. 9.3.4 Current Limit
      5. 9.3.5 Output Discharge
      6. 9.3.6 Input and Output Capacitance
      7. 9.3.7 Power Dissipation and Junction Temperature
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation with VIN < 4 V (Minimum VIN)
      2. 9.4.2 Operation With EN Control
      3. 9.4.3 Operation of Level 4 IEC61000-4-2 ESD Protection
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 USB2.0 Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 USB3.0 Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 商标
    3. 13.3 静电放电警告
    4. 13.4 术语表
  14. 14机械封装和可订购信息

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机械数据 (封装 | 引脚)
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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

TPD3S0x4 are devices that feature a current limited load switch and a two channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array. They are typically used to provide a complete protection solution for USB host ports. USB host ports are required by the USB specification to provide a current limit on the VBUS path in order to protect the system from over-current conditions on the port that could lead to system damage and user injury. Additionally, USB ports typically require system level IEC ESD protection due to direct end-user interaction. The following design procedure can be used to determine how to properly implement TPD3S0x4s in your systems to provide a complete, one-chip solution for your USB ports.

10.2 Typical Application

10.2.1 USB2.0 Application

TPD3S014 TPD3S044 TPD3S0x4_Typ_Application_FAD_14.gifFigure 32. USB2.0 Application Schematic

10.2.1.1 Design Requirements

For this design example, use the following as the system parameters.

DESIGN PARAMETER VALUE
USB Port Type Standard Downstream Port
Signal Voltage Range on VBUS 0 V to 5.25 V
Current Range on VBUS 0 mA to 500 mA
Maximum Voltage Droop Allowed on Adjacent USB Port 330 mV
Maximum Data Rate 480 Mbps

10.2.1.2 Detailed Design Procedure

To properly implement your USB port with TPD3S0x4s, the first step is to determine what type of USB port you are implementing in your system, whether it be a Standard Downstream Port (SDP), Charging Downstream Port (CDP), or Dedicated Charging Port (DCP); this will inform you what your maximum continuous operating current will be on VBUS. In our example, we are implementing an SDP port, so the maximum continuous current allowed to be pulled by a device is 500mA. Therefore, we need to choose a current limit switch that is 5.25V tolerant, can handle 500mA continuous DC current, and has a current limit point is above 500 mA so it will not current limit during normal operation. TPD3S014 is therefore the best choice for this application, as it has these features, and in fact was specifically designed for this application.

The next decision point is choosing your input and output capacitors for your current limit switch. A minimum of 0.1 µF is always recommended on the IN pin. For the OUT pin on VBUS, USB standard requires a minimum of 120 µF; typically a 150 µF capacitor is used. The purpose of the capacitance requirement on the VBUS line in the USB specification is to prevent the adjacent USB port's VBUS voltage from dropping more than 330 mV during a hot-plug or fault occurrence on the VBUS pin of one USB port. Hot-plugs and fault conditions on one USB port should not disturb the normal operation of an adjacent USB port; therefore, it is possible to use an output capacitance lower than 120 µF if your system is able to keep voltage droops on adjacent USB ports less than or equal to 330 mV. For example, if the DC/DC powering VBUS has a fast transient response, 120 µF may not be required.

If your USB port is powered from a shared system 5V rail, a system designer may desire to use large than 0.1 µF for the input capacitor on the IN pin. This is largely dependent on your PCB layout and parasitics, as well as your maximum tolerated voltage droop on the shared rail during transients. For more information on choosing input and output capacitors, please see Input and Output Capacitance in the Detailed Description section.

The EN pin controls the on and off state of the device, and typically is connected to the system processor for power sequencing. However, the EN pin can also be shorted to the IN pin to always have the TPD3S014 on when 5V power supply on; this also saves a GPIO pin on your processor.

For a USB port with High-Speed 480Mbps operation, low capacitance TVS ESD protection diodes are required to protect the D+ and D- lines in the event of system level ESD event. TPD3S014 has 2-channels of low capacitance TVS ESD protection diodes integrated. When placed near the USB connector, TPD3S014 offers little or no signal distortion during normal operation. TPD3S014 also ensures that the core system circuitry is protected in the event of an ESD strike. PCB Layout is critical when implementing TVS ESD protection diodes in your system; please read the Layout section for proper guidelines on routing your USB lines with TPD3S014.

10.2.1.3 Application Curves

TPD3S014 TPD3S044 TPD3S0x4_Eye_NoEVM.gifFigure 33. Eye-Diagram Without EVM
TPD3S014 TPD3S044 TPD3S0x4_Eye_EVM.gifFigure 35. Eye-Diagram of TPD3S0x4 on EVM
TPD3S014 TPD3S044 TPD3S0x4_Eye_EVM_UnPop.gifFigure 34. Eye-Diagram With EVM, Without TPD3S0x4

10.2.2 USB3.0 Application

TPD3S014 TPD3S044 typ_app_slvscp4.gifFigure 36. USB3.0 Application Schematic

10.2.2.1 Design Requirements

For this design example, use the following as the system parameters.

DESIGN PARAMETER VALUE
USB Port Type Standard Downstream Port
Signal Voltage Range on VBUS 0 V to 5.25 V
Current Range on VBUS 0 mA to 900 mA
Maximum Voltage Droop Allowed on Adjacent USB Port 330 mV
Maximum Data Rate D+, D- Lines 480 Mbps
Maximum Data Rate TX+/-, RX+/- Lines 5 Gbps

10.2.2.2 Detailed Design Procedure

The implementation of the USB3.0 port with TPD3S0x4s is identical to the USB2.0 port, except that in this use case we must use TPD3S044 because USB3.0 SDP has a maximum VBUS current 900 mA. TPD3S014 current limit level is too low for USB3.0 operation. In addition to using TPD3S044, USB3.0 has four more Super-Speed Lines for transferring data 5 Gbps, and these lines also typically require Level 4 IEC61000-4-2 ESD Protection. With a data rate of 5 Gbps, ultra-low capacitance TVS ESD protection diodes are required to protect the TX+/– and RX+/– lines in the event of system level ESD event. TPD4E05U06 provides 4-channels of ultra-low capacitance TVS ESD protection diodes for USB3.0 Super-Speed lines, and can be coupled with TPD3S044 to provide a two-chip total protection solution for the USB3.0 Host Port. Please refer to the Layout section of the datasheet for guidelines on the PCB Layout of this two-chip solution.

The rest of the design procedure is identical to the USB2.0 Application section, so please refer to it for the rest of the design procedure.

10.2.2.3 Application Curves

See Application Curves for TPD3S0x4 Eye-Diagram performance. Please refer to the TPD4E05U06 datasheet on ti.com to see its specifications and Eye-Diagram performance.