SLVS639F October   2007  – February 2016 TPD12S521

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Circuit Protection Scheme
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Single-Chip ESD Solution for HDMI Driver
      2. 8.3.2 Supports All HDMI 1.3 and HDMI 1.4b Data Rates
      3. 8.3.3 Integrated Level Shifting for the Control Lines
      4. 8.3.4 ±8-kV Contact ESD Protection on External Lines
      5. 8.3.5 38-Pin TSSOP Provides Seamless Layout Option With HDMI Connector
      6. 8.3.6 Backdrive Protection
      7. 8.3.7 Lead-Free Package
      8. 8.3.8 On-Chip Current Regulator With 55-mA Current Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DBT|38
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)(2)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V5V_SUPPLY Supply voltage –0.3 6 V
VLV_SUPPLY
VI/O DC voltage at any channel input –0.5 6 V
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per MIL-STD-883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ(1) Pins 1, 2, 16–19, 37, 38 ±2000 V
IEC 61000-4-2 Contact Discharge(2) Pins 4, 7, 10, 13, 20–24, 27, 30, 33 ±8000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
TA Operating free-air temperature –40 85 °C
5V_SUPPLY Operating supply voltage 5 5.5 V
LV_SUPPLY Bias supply voltage 1 3.3 5.5 V

7.4 Thermal Information

THERMAL METRIC(1) TPD12S521 UNIT
DBT
38 PINS
RθJA Junction-to-ambient thermal resistance 83.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.8
RθJB Junction-to-board thermal resistance 44.7
ψJT Junction-to-top characterization parameter 2.9
ψJB Junction-to-board characterization parameter 44.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC5 Operating supply current 5V_SUPPLY = 5 V 110 130 µA
ICC3 Bias supply current LV_SUPPLY = 3.3 V 1 5 µA
VDROP 5V_OUT overcurrent output drop 5V_SUPPLY = 5 V, IOUT = 55 mA 150 200 mV
ISC 5V_OUT short-circuit current limit 5V_SUPPLY= 5 V, 5V_OUT = GND 90 135 175 mA
IOFF OFF-state leakage current, level-shifting NFET LV_SUPPLY = 0 V 0.1 5 µA
IBACK DRIVE Current conducted from output pins to V_SUPPLY rails when powered down 5V_SUPPLY < VCH_OUT TMDS_D[2:0]+/–,

TMDS_CK+/–,

CE_REMOTE_OUT,

DDC_DAT_OUT,

DDC_CLK_OUT,

HOTPLUG_DET_OUT

 0.1 5 µA
VON Voltage drop across level-shifting NFET when ON LV_SUPPLY = 2.5 V, VS = GND, IDS = 3 mA 75 95 140 mV
VF Diode forward voltage IF = 8 mA, Top diode 0.85 V
TA = 25°C(1) Bottom diode 0.85
VCL Channel clamp voltage at ±8 kV HBM ESD TA = 25°C(1)(2) Positive transients 9 V
Negative transients -9
RDYN Dynamic resistance I = 1 A, TA = 25°C(3) Positive transients 3 Ω
Negative transients 1.5
ILEAK TMDS channel leakage current TA = 25°C(1) 0.01 1 µA
CIN,

TMDS

TMDS channel input capacitance 5V_SUPPLY= 5 V, Measured at 1 MHz,

VBIAS = 2.5 V(1)

0.8 1.0 pF
ΔCIN,

TMDS

 TMDS channel input capacitance matching 5V_SUPPLY= 5 V, Measured at 1 MHz,

VBIAS = 2.5 V(1)(4)

0.05 pF
CMUTUAL Mutual capacitance between signal pin and adjacent signal pin 5V_SUPPLY= 0 V, Measured at 1 MHz,

VBIAS = 2.5 V(1)

0.07 pF
CIN Level-shifting input capacitance, capacitance to GND 5V_SUPPLY= 0 V, Measured at 100 KHz,

VBIAS = 2.5 V(1)

DDC 3.5 4 pF
CEC 3.5 4
HP 3.5 4
(1) This parameter is specified by design and verified by device characterization
(2) Human-Body Model (HBM) per MIL-STD-883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ
(3) These measurements performed with no external capacitor on ESD_BYP.
(4) Intrapair matching, each TMDS pair (i.e., D+, D–)

7.6 Typical Characteristics

TPD12S521 ilGraph.eps
Figure 1. Insertion Loss Performance Across Frequency