ZHCSOX0A March   2023  – September 2023 TMUX6221 , TMUX6222

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Source or Drain Continuous Current
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 6.7  ±15 V Dual Supply: Switching Characteristics 
    8. 6.8  36 V Single Supply: Electrical Characteristics 
    9. 6.9  36 V Single Supply: Switching Characteristics 
    10. 6.10 12 V Single Supply: Electrical Characteristics 
    11. 6.11 12 V Single Supply: Switching Characteristics 
    12. 6.12 ±5 V Dual Supply: Electrical Characteristics 
    13. 6.13 ±5 V Dual Supply: Switching Characteristics 
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  tON(EN) and tOFF(EN)
    5. 7.5  tON (VDD) Time
    6. 7.6  Propagation Delay
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
    11. 7.11 THD + Noise
    12. 7.12 Power Supply Rejection Ratio (PSRR)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Latch-Up Immune
      7. 8.3.7 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Switched Gain Amplifier – Discrete PGA
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DGS|10
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VDD – VSS Supply voltage 38 V
VDD –0.5 38 V
VSS –38 0.5 V
VSEL or VEN Logic control input pin voltage (SELx) –0.5 38 V
ISEL or IEN Logic control input pin current (SELx) –30 30 mA
VS or VD Source or drain voltage (Sx, Dx) VSS–0.5 VDD+0.5 V
IIK  Diode clamp current(3) –30 30 mA
IS or ID (CONT) Source or drain continuous current (Sx, Dx) IDC + 10 %(4) mA
TA Ambient temperature –55 150 °C
Tstg Storage temperature –65 150 °C
TJ Junction temperature 150 °C
Ptot Total power dissipation (VSSOP)(5) 450 mW
(1) Operation outside the Absolute Maximum Rating may cause permanent device damage. Absolute Maximum Rating do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Condition. If used outside the Recommended Operating Condition but within the Absolute Maximum Rating, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
(4) Refer to Source or Drain Continuous Current table for IDC specifications.
(5) For VSSOP package: Ptot derates linearly above TA = 70°C by 6.7mW/°C.