SLVSA61H February   2010  – August 2016

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Dropout Voltage
      4. 7.3.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN Less than 2 V
      2. 7.4.2 Operation With VIN Greater than 2 V
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Requirements
      2. 8.1.2 Transient Response
      3. 8.1.3 Thermal Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitance
        2. 8.2.2.2 Output Capacitance
        3. 8.2.2.3 Thermal Calculation
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

At TA = –40°C to 125°C (unless otherwise noted). All voltages are with respect to GND.(1)
MIN MAX UNIT
VIN Input voltage –0.3 6 V
VEN Enable voltage –0.3 6 V
VOUT Output voltage –0.3 6 V
IOUT Maximum output current Internally limited
Output short-circuit duration Indefinite
TJ Operating ambient temperature –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input supply-voltage range 2 5.5 V
VOUT Output voltage 1.2 4.8 V
IOUT Oytput current 0 200 mA
VEN Voltage on EN pin 0 VIN V
TA Operating ambient temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TLV700xx-Q1 UNIT
DCK (SOT) DDC (SOT)
5 Pins 5 PINS
RθJA Junction-to-ambient thermal resistance 307.6 262.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 79.1 68.2 °C/W
RθJB Junction-to-board thermal resistance 93.7 81.6 °C/W
ψJT Junction-to-top characterization parameter 1.3 1.1 °C/W
ψJB Junction-to-board characterization parameter 92.8 80.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VIN = VOUT(TYP) + 0.3 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to 125°C (unless otherwise noted). Typical values are at TA = 25°C.
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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT DC output accuracy –40°C ≤ TA ≤ 125°C VOUT ≥ 1 V –2% 2%
VOUT < 1 V –20 20 mV
ΔVO / ΔVIN Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V
IOUT = 10 mA
1 5 mV
ΔVO / ΔIOUT Load regulation 0 mA ≤ IOUT ≤ 200 mA, TLV70025-Q1
TLV70030-Q1, TLV70033-Q1
15 mV
0 mA ≤ IOUT ≤ 200 mA, TLV70012A-Q1 20
VDO Dropout voltage(1) VIN = 0.98 × VOUT(NOM), IOUT = 200 mA 175 250 mV
ICL Output current limit VOUT = 0.9 × VOUT(NOM) 220 350 550 mA
IGND Ground pin current IOUT = 0 mA 31 55 μA
IOUT = 200 mA, VIN = VOUT + 0.5 V 270 μA
ISHDN Ground pin current (shutdown) VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V 1 2.5 μA
PSRR Power-supply rejection ratio VIN = 2.3 V, VOUT = 1.8 V
IOUT = 10 mA, f = 1 kHz
68 dB
VN Output noise voltage BW = 100 Hz to 100 kHz
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
48 μVRMS
tSTR Startup time(2) COUT = 1 μF, IOUT = 200 mA 100 μs
VEN(HI) Enable pin high (enabled) 0.9 VIN V
VEN(LO) Enable pin low (disabled) 0 0.4 V
IEN Enable pin current VEN = 5.5 V , IOUT = 10 μA 0.04 0.5 μA
UVLO Undervoltage lockout VIN rising 1.9 V
TSD Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140 °C
TA Operating ambient temperature –40 125 °C
(1) VDO is measured for devices with VOUT(NOM) ≥ 2.35 V.
(2) Startup time = time from EN assertion to 0.98 × VOUT(NOM).

6.6 Typical Characteristics

TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless otherwise noted). Typical values are at TJ = 25°C.
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_line_reg_10ma_lvsa00.gif
Figure 1. TLV700xx-Q1 Line Regulation
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_load_reg_018_lvsa00.gif
Figure 3. TLV700xx-Q1 Load Regulation
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_vdo_iout_lvsa00.gif
Figure 5. TLV700xx-Q1 Dropout Voltage vs Output Current
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_ignd_vin_0ma_lvsa00.gif
Figure 7. TLV700xx-Q1 Ground Pin Current vs Input Voltage
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_ignd_temp_lvsa00.gif
Figure 9. TLV70018 Ground Pin Current vs Temperature
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_ilim_vin_lvsa00.gif
Figure 11. TLV700xx-Q1 Current Limit vs Input Voltage
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_psrr_vin_lvsa00.gif
Figure 13. TLV700xx-Q1 Power-Supply Ripple Rejection vs Input Voltage
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_load_tr_150_lvsa00.gif
Figure 15. TLV700xx-Q1 Load Transient Response
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_load_tr_50_lvsa00.gif
Figure 17. TLV700xx-Q1 Load Transient Response
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_line_tr_1_lvsa00.gif
Figure 19. TLV700xx-Q1 Line Transient Response
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_pupd_lvsa00.gif
Figure 21. TLV700xx-Q1 VIN Ramp-Up, Ramp-Down Response
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_line_reg_200ma_lvsa00.gif
Figure 2. TLV700xx-Q1 Line Regulation
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_vdo_vin_lvsa00.gif
Figure 4. TLV700xx-Q1 Dropout Voltage vs Input Voltage
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_vout_temp_lvsa00.gif
Figure 6. TLV700xx-Q1 Output Voltage vs Temperature
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_ignd_load_lvsa00.gif
Figure 8. TLV700xx-Q1 Ground Pin Current vs Load
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_ishut_vin_lvsa00.gif
Figure 10. TLV700xx-Q1 Shutdown Current vs Input Voltage
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_psrr_fqcy_05v_lvsa00.gif
Figure 12. TLV700xx-Q1 Power-Supply Ripple Rejection vs Frequency
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_output_spec_noise_lvsa00.gif
Figure 14. TLV700xx-Q1 Output Spectral Noise Density vs Output Voltage
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_load_tr_10_lvsa00.gif
Figure 16. TLV700xx-Q1 Load Transient Response
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_line_tr_200-1_lvsa00.gif
Figure 18. TLV700xx-Q18 Line Transient Response
TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 tc_line_tr_200-2_lvsa00.gif
Figure 20. TLV700xx-Q1 Line Transient Response