ZHCS484H October   2011  – January 2017 TLV62080 , TLV62084 , TLV62084A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5  Device Comparison Table
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 100% Duty-Cycle Low-Dropout Operation
      2. 8.3.2 Enabling and Disabling the Device
      3. 8.3.3 Output Discharge
      4. 8.3.4 Soft Start
      5. 8.3.5 Power Good
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Thermal Shutdown
      8. 8.3.8 Inductor Current-Limit
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Save Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Output Filter Design
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Capacitor Selection
        5. 9.2.2.5 Setting the Output Voltage
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 开发支持
        1. 12.1.2.1 使用 WEBENCH® 工具定制设计方案
    2. 12.2 文档支持
    3. 12.3 相关链接
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 接收文档更新通知
    7. 12.7 社区资源
    8. 12.8 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Layout

11.1 Layout Guidelines

The PCB layout is an important step to maintain the high performance of the TLV62080 and TLV62084x devices.

  • Place input and output capacitors, along with the inductor, as close as possible to the IC which keeps the traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
  • Use a common-power GND.
  • Properly connect the low side of the input and output capacitors to the power GND to avoid a GND potential shift.
  • The sense traces connected to FB and VOS terminals are signal traces. Keep these traces away from SW nodes.
  • Use care to avoid noise induction. By a direct routing, parasitic inductance can be kept small.
  • Use GND layers for shielding if needed.

11.2 Layout Example

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TLV62080 TLV62084 TLV62084A SLVSAK9_layout_new.gif Figure 18. PCB Layout Suggestion

11.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below:

  • Improving the power dissipation capability of the PCB design.
  • Improving the thermal coupling of the component to the PCB by soldering the Thermal Pad.
  • Introducing airflow in the system.

For more details on how to use the thermal parameters, see the Thermal Characteristics application notes SZZA017 and SPRA953.