SLAS663C August   2009  – June 2016 TLV320AIC3106-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Switching Characteristics I2S/LJF/RJF In Master Mode
    7. 8.7  Switching Characteristics I2S/LJF/RJF In Slave Mode
    8. 8.8  Switching Characteristics DSP In Master Mode
    9. 8.9  Switching Characteristics DSP In Slave Mode
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Audio Data Converters
      2. 9.3.2  Stereo Audio ADC
        1. 9.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 9.3.3  Automatic Gain Control (AGC)
      4. 9.3.4  Stereo Audio DAC
      5. 9.3.5  Digital Audio Processing For Playback
      6. 9.3.6  Digital Interpolation Filter
      7. 9.3.7  Delta-Sigma Audio Dac
      8. 9.3.8  Audio Dac Digital Volume Control
      9. 9.3.9  Analog Output Common-Mode Adjustment
      10. 9.3.10 Audio DAC Power Control
      11. 9.3.11 Audio Analog Inputs
      12. 9.3.12 Analog Input Bypass Path Functionality
      13. 9.3.13 ADC PGA Signal Bypass Path Functionality
      14. 9.3.14 Input Impedance and VCM Control
      15. 9.3.15 MICBIAS Generation
      16. 9.3.16 Analog Fully Differential Line Output Drivers
      17. 9.3.17 Analog High Power Output Drivers
      18. 9.3.18 Short Circuit Output Protection
      19. 9.3.19 Jack and Headset Detection
      20. 9.3.20 General-Purpose I/O
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Audio Processing For Record Path
      2. 9.4.2 Increasing DAC Dynamic Range
      3. 9.4.3 Passive Analog Bypass During Powerdown
      4. 9.4.4 Digital Microphone Connectivity
    5. 9.5 Programming
      1. 9.5.1  Hardware Reset
      2. 9.5.2  Digital Control Serial Interface
        1. 9.5.2.1 SPI Control Mode
        2. 9.5.2.2 SPI Communication Protocol
          1. 9.5.2.2.1 Limitation On Register Writing
        3. 9.5.2.3 Continuous Read and Write Operation
      3. 9.5.3  I2C Control Mode
      4. 9.5.4  I2C Bus Debug In A Glitched System
      5. 9.5.5  Digital Audio Data Serial Interface
      6. 9.5.6  Right-Justified Mode
      7. 9.5.7  Left-Justified Mode
      8. 9.5.8  I2S Mode
      9. 9.5.9  DSP Mode
      10. 9.5.10 TDM Data Transfer
      11. 9.5.11 Audio Clock Generation
    6. 9.6 Register Maps
      1. 9.6.1 Output Stage Volume Controls
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, And Orderable Information

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7 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
Solder the VQFN thermal pad to the ground plane (DRVSS).

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVDD_DAC 25 I Analog DAC voltage supply, 2.7 V to 3.6 V
AVSS_ADC 15 I Analog ADC ground supply, 0 V
AVSS_DAC 26 I Analog DAC ground supply, 0 V
BCLK 38 I/O Audio serial data bus bit clock (I/O)
DIN 40 i Audio serial data bus data input
DOUT 41 O Audio serial data bus data output
DRVDD 16,17 I ADC analog and output driver voltage supply, 2.7 V to 3.6 V
DRVDD 24 I ADC analog and output driver voltage supply, 2.7 V to 3.6 V
DRVSS 20, 21 I Analog output driver ground supply, 0 V
DVDD 36 I Digital core voltage supply, 1.65 V to 1.95 V
DVSS 42 I Digital core and I/O ground supply, 0 V
GPIO1 35 I/O General-purpose I/O 1: input and output, PLL, clock mux output, short circuit interrupt, AGC noise flag, or digital microphone clock audio serial data bus word clock
GPIO2 34 I/O General-purpose I/O 2: input and output, digital microphone data input, PLL clock input, or audio serial data bus bit clock
HPLOUT 18 O High-power output driver (left+)
HPLCOM 19 O High-power output driver (left– or multifunctional)
HPRCOM 22 O High-power output driver (right– or multifunctional)
HPROUT 23 O High-power output driver (right+)
IOVDD 44 I I/O voltage supply, 1.1 V to 3.6 V
LEFT_LOM 30 O Left line output (–)
LEFT_LOP 29 O Left line output (+)
LINE1LM 4 I MIC1 or Line1 analog input (left– or multifunction)
LINE1LP 3 I MIC1 or Line1 analog input (left+ or multifunction)
LINE1RM 6 I MIC1 or Line1 analog input (right– or multifunction)
LINE1RP 5 I MIC1 or Line1 analog input (right+ or multifunction)
LINE2LM 8 I MIC2 or Line2 analog input (left– or multifunction)
LINE2LP 7 I MIC2 or Line2 analog input (left+ or multifunction)
LINE2RM 10 I MIC2 or Line2 analog input (right– or multifunction)
LINE2RP 9 I MIC2 or Line2 analog input (right+ or multifunction)
MCLK 37 I Master clock input
MIC3L 11 I MIC3 input (left or multifunction)
MIC3R 14 I MIC3 input (right or multifunction)
MICBIAS 13 O Microphone bias voltage output
MICDET 12 I Microphone detect
MFP0 45 I/O Multifunction pin 0. SPI chip select, GPI, or I2C address pin #0
MFP1 46 I/O Multifunction pin 1. SPI serial clock, GPI, or I2C address pin #1S
MFP2 47 I/O Multifunction pin 2. SPI MISO slave serial data output or GPIO
MFP3 48 I/O Multifunction pin 3. SPI MOSI slave serial data input, GPI, or audio serial data bus data input
MONO_LOM 28 O Mono line output (–)
MONO_LOP 27 O Mono line output (+)
RESET 33 I Reset. Active low
RIGHT_LOM 32 O Right line output (–)
RIGHT_LOP 31 O Right line output (+)
SCL 1 I/O I2C serial clock or GPIO
SDA 2 I/O I2C serial data input and output or GPIO
SELECT 43 I Control mode select pin (1 = SPI, 0 = I2C)
WCLK 39 I/O Audio serial data bus word clock (I/O)