ZHCSMM8A December 2020 – June 2021 TLV320ADC3120
PRODUCTION DATA
Table 8-51 lists the memory-mapped registers for the Page 0 registers. All register offset addresses not listed in Table 8-51 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Reset Value | Section |
---|---|---|---|---|
0x0 | PAGE_CFG | Device page register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_PAGE_CFG |
0x1 | SW_RESET | Software reset register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_SW_RESET |
0x2 | SLEEP_CFG | Sleep mode register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_SLEEP_CFG |
0x5 | SHDN_CFG | Shutdown configuration register | 0x05 | #TLV320ADC3120_PAGE_0_PAGE_0_SHDN_CFG |
0x7 | ASI_CFG0 | ASI configuration register 0 | 0x30 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_CFG0 |
0x8 | ASI_CFG1 | ASI configuration register 1 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_CFG1 |
0x9 | ASI_CFG2 | ASI configuration register 2 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_CFG2 |
0xA | ASI_MIX_CFG | ASI input mixing configuration register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_MIX_CFG |
0xB | ASI_CH1 | Channel 1 ASI slot configuration register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_CH1 |
0xC | ASI_CH2 | Channel 2 ASI slot configuration register | 0x01 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_CH2 |
0xD | ASI_CH3 | Channel 3 ASI slot configuration register | 0x02 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_CH3 |
0xE | ASI_CH4 | Channel 4 ASI slot configuration register | 0x03 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_CH4 |
0x13 | MST_CFG0 | ASI master mode configuration register 0 | 0x02 | #TLV320ADC3120_PAGE_0_PAGE_0_MST_CFG0 |
0x14 | MST_CFG1 | ASI master mode configuration register 1 | 0x48 | #TLV320ADC3120_PAGE_0_PAGE_0_MST_CFG1 |
0x15 | ASI_STS | ASI bus clock monitor status register | 0xFF | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_STS |
0x16 | CLK_SRC | Clock source configuration register 0 | 0x10 | #TLV320ADC3120_PAGE_0_PAGE_0_CLK_SRC |
0x1F | PDMCLK_CFG | PDM clock generation configuration register | 0x40 | #TLV320ADC3120_PAGE_0_PAGE_0_PDMCLK_CFG |
0x20 | PDMIN_CFG | PDM DINx sampling edge register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_PDMIN_CFG |
0x21 | GPIO_CFG0 | GPIO configuration register 0 | 0x22 | #TLV320ADC3120_PAGE_0_PAGE_0_GPIO_CFG0 |
0x22 | GPO_CFG0 | GPO configuration register 0 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_GPO_CFG0 |
0x29 | GPO_VAL | GPIO, GPO output value register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_GPO_VAL |
0x2A | GPIO_MON | GPIO monitor value register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_GPIO_MON |
0x2B | GPI_CFG0 | GPI configuration register 0 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_GPI_CFG0 |
0x2F | GPI_MON | GPI monitor value register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_GPI_MON |
0x32 | INT_CFG | Interrupt configuration register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_INT_CFG |
0x33 | INT_MASK0 | Interrupt mask register 0 | 0xFF | #TLV320ADC3120_PAGE_0_PAGE_0_INT_MASK0 |
0x36 | INT_LTCH0 | Latched interrupt readback register 0 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_INT_LTCH0 |
0x3A | CM_TOL_CFG | ADC common mode configuration register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CM_TOL_CFG |
0x3B | BIAS_CFG | Bias and ADC configuration register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_BIAS_CFG |
0x3C | CH1_CFG0 | Channel 1 configuration register 0 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CH1_CFG0 |
0x3D | CH1_CFG1 | Channel 1 configuration register 1 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CH1_CFG1 |
0x3E | CH1_CFG2 | Channel 1 configuration register 2 | 0xC9 | #TLV320ADC3120_PAGE_0_PAGE_0_CH1_CFG2 |
0x3F | CH1_CFG3 | Channel 1 configuration register 3 | 0x80 | #TLV320ADC3120_PAGE_0_PAGE_0_CH1_CFG3 |
0x40 | CH1_CFG4 | Channel 1 configuration register 4 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CH1_CFG4 |
0x41 | CH2_CFG0 | Channel 2 configuration register 0 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CH2_CFG0 |
0x42 | CH2_CFG1 | Channel 2 configuration register 1 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CH2_CFG1 |
0x43 | CH2_CFG2 | Channel 2 configuration register 2 | 0xC9 | #TLV320ADC3120_PAGE_0_PAGE_0_CH2_CFG2 |
0x44 | CH2_CFG3 | Channel 2 configuration register 3 | 0x80 | #TLV320ADC3120_PAGE_0_PAGE_0_CH2_CFG3 |
0x45 | CH2_CFG4 | Channel 2 configuration register 4 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CH2_CFG4 |
0x48 | CH3_CFG2 | Channel 3 configuration register 2 | 0xC9 | #TLV320ADC3120_PAGE_0_PAGE_0_CH3_CFG2 |
0x49 | CH3_CFG3 | Channel 3 configuration register 3 | 0x80 | #TLV320ADC3120_PAGE_0_PAGE_0_CH3_CFG3 |
0x4A | CH3_CFG4 | Channel 3 configuration register 4 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CH3_CFG4 |
0x4D | CH4_CFG2 | Channel 4 configuration register 2 | 0xC9 | #TLV320ADC3120_PAGE_0_PAGE_0_CH4_CFG2 |
0x4E | CH4_CFG3 | Channel 4 configuration register 3 | 0x80 | #TLV320ADC3120_PAGE_0_PAGE_0_CH4_CFG3 |
0x4F | CH4_CFG4 | Channel 4 configuration register 4 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_CH4_CFG4 |
0x6B | DSP_CFG0 | DSP configuration register 0 | 0x01 | #TLV320ADC3120_PAGE_0_PAGE_0_DSP_CFG0 |
0x6C | DSP_CFG1 | DSP configuration register 1 | 0x40 | #TLV320ADC3120_PAGE_0_PAGE_0_DSP_CFG1 |
0x70 | AGC_CFG0 | AGC configuration register 0 | 0xE7 | #TLV320ADC3120_PAGE_0_PAGE_0_AGC_CFG0 |
0x71 | GAIN_CFG | Gain change Configuration | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_GAIN_CFG |
0x73 | IN_CH_EN | Input channel enable configuration register | 0xC0 | #TLV320ADC3120_PAGE_0_PAGE_0_IN_CH_EN |
0x74 | ASI_OUT_CH_EN | ASI output channel enable configuration register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_ASI_OUT_CH_EN |
0x75 | PWR_CFG | Power up configuration register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_PWR_CFG |
0x76 | DEV_STS0 | Device status value register 0 | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_DEV_STS0 |
0x77 | DEV_STS1 | Device status value register 1 | 0x80 | #TLV320ADC3120_PAGE_0_PAGE_0_DEV_STS1 |
0x7E | I2C_CKSUM | I2C checksum register | 0x00 | #TLV320ADC3120_PAGE_0_PAGE_0_I2C_CKSUM |
PAGE_CFG is shown in Figure 8-71 and described in Table 8-52.
Return to the Summary Table.
The device memory map is divided into pages. This register sets the page.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PAGE[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PAGE[7:0] | R/W | 00000000b | These bits set the device page.
0d = Page 0 1d = Page 1 2d to 254d = Page 2 to page 254 respectively 255d = Page 255 |
SW_RESET is shown in Figure 8-72 and described in Table 8-53.
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This register is the software reset register. Asserting a software reset places all register values in their default power-on-reset (POR) state.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SW_RESET | ||||||
R-0000000b | R/W-0b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | RESERVED | R | 0000000b | Reserved bits; Write only reset value |
0 | SW_RESET | R/W | 0b | Software reset. This bit is self clearing.
0d = Do not reset 1d = Reset all registers to their reset values |
SLEEP_CFG is shown in Figure 8-73 and described in Table 8-54.
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This register configures the regulator, VREF quick charge, I2C broadcast and sleep mode.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AREG_SELECT | RESERVED | VREF_QCHG[1:0] | I2C_BRDCAST_EN | RESERVED | SLEEP_ENZ | ||
R/W-0b | R/W-00b | R/W-00b | R/W-0b | R-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AREG_SELECT | R/W | 0b | The analog supply selection from either the internal regulator supply or the external AREG supply.
0d = External 1.8-V AREG supply (use this setting when AVDD is 1.8 V and short AREG with AVDD) 1d = Internally generated 1.8-V AREG supply using an on-chip regulator (use this setting when AVDD is 3.3 V) |
6-5 | RESERVED | R/W | 00b | Reserved bits; Write only reset values |
4-3 | VREF_QCHG[1:0] | R/W | 00b | The duration of the quick-charge for the VREF external capacitor is set using an internal series impedance of 200 Ω.
0d = VREF quick-charge duration of 3.5 ms (typical) 1d = VREF quick-charge duration of 10 ms (typical) 2d = VREF quick-charge duration of 50 ms (typical) 3d = VREF quick-charge duration of 100 ms (typical) |
2 | I2C_BRDCAST_EN | R/W | 0b | I2C broadcast addressing setting.
0d = I2C broadcast mode disabled 1d = I2C broadcast mode enabled; the I2C slave address is fixed at 1001 100 |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | SLEEP_ENZ | R/W | 0b | Sleep mode setting.
0d = Device is in sleep mode 1d = Device is not in sleep mode |
SHDN_CFG is shown in Figure 8-74 and described in Table 8-55.
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This register configures the device shutdown
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INCAP_QCHG[1:0] | RESERVED | RESERVED | ||||
R-00b | R/W-00b | R/W-01b | R/W-01b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved bits; Write only reset value |
5-4 | INCAP_QCHG[1:0] | R/W | 00b | The duration of the quick-charge for the external AC-coupling capacitor is set using an internal series impedance of 800 Ω.
0d = INxP, INxM quick-charge duration of 2.5 ms (typical) 1d = INxP, INxM quick-charge duration of 12.5 ms (typical) 2d = INxP, INxM quick-charge duration of 25 ms (typical) 3d = INxP, INxM quick-charge duration of 50 ms (typical) |
3-2 | RESERVED | R/W | 01b | Reserved bits; Write only reset values |
1-0 | RESERVED | R/W | 01b | Reserved bits; Write only reset values |
ASI_CFG0 is shown in Figure 8-75 and described in Table 8-56.
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This register is the ASI configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASI_FORMAT[1:0] | ASI_WLEN[1:0] | FSYNC_POL | BCLK_POL | TX_EDGE | TX_FILL | ||
R/W-00b | R/W-11b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | ASI_FORMAT[1:0] | R/W | 00b | ASI protocol format.
0d = TDM mode 1d = I2S mode 2d = LJ (left-justified) mode 3d = Reserved; Don't use |
5-4 | ASI_WLEN[1:0] | R/W | 11b | ASI word or slot length.
0d = 16 bits (Recommended this setting to be used with 10-kΩ or 20-kΩ input impedance configuration) 1d = 20 bits 2d = 24 bits 3d = 32 bits |
3 | FSYNC_POL | R/W | 0b | ASI FSYNC polarity.
0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol |
2 | BCLK_POL | R/W | 0b | ASI BCLK polarity.
0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol |
1 | TX_EDGE | R/W | 0b | ASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in bit 2 (BCLK_POL) 1d = Inverted following edge (half cycle delay) with respect to the default edge setting |
0 | TX_FILL | R/W | 0b | ASI data output (on the primary and secondary data pin) for any unused cycles
0d = Always transmit 0 for unused cycles 1d = Always use Hi-Z for unused cycles |
ASI_CFG1 is shown in Figure 8-76 and described in Table 8-57.
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This register is the ASI configuration register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_LSB | TX_KEEPER[1:0] | TX_OFFSET[4:0] | |||||
R/W-0b | R/W-00b | R/W-00000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TX_LSB | R/W | 0b | ASI data output (on the primary and secondary data pin) for LSB transmissions.
0d = Transmit the LSB for a full cycle 1d = Transmit the LSB for the first half cycle and Hi-Z for the second half cycle |
6-5 | TX_KEEPER[1:0] | R/W | 00b | ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled 1d = Bus keeper is always enabled 2d = Bus keeper is enabled during LSB transmissions only for one cycle 3d = Bus keeper is enabled during LSB transmissions only for one and half cycles |
4-0 | TX_OFFSET[4:0] | R/W | 00000b | ASI data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol 1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol 2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol 3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration 31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol |
ASI_CFG2 is shown in Figure 8-77 and described in Table 8-58.
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This register is the ASI configuration register 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASI_DAISY | RESERVED | ASI_ERR | ASI_ERR_RCOV | RESERVED | RESERVED | ||
R/W-0b | R-0b | R/W-0b | R/W-0b | R/W-0b | R-000b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ASI_DAISY | R/W | 0b | ASI daisy chain connection.
0d = All devices are connected in the common ASI bus 1d = All devices are daisy-chained for the ASI bus. This is supported only if ASI input mixing is disabled, refer register 10 for details on ASI input mixing feature. |
6 | RESERVED | R | 0b | Reserved bit; Write only reset value |
5 | ASI_ERR | R/W | 0b | ASI bus error detection.
0d = Enable bus error detection 1d = Disable bus error detection |
4 | ASI_ERR_RCOV | R/W | 0b | ASI bus error auto resume.
0d = Enable auto resume after bus error recovery 1d = Disable auto resume after bus error recovery and remain powered down until the host configures the device |
3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
2-0 | RESERVED | R | 000b | Reserved bits; Write only reset value |
ASI_MIX_CFG is shown in Figure 8-78 and described in Table 8-59.
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This register is the ASI input mixing configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASI_MIX_SEL[1:0] | ASI_GAIN_SEL[1:0] | ASI_IN_INVERSE | RESERVED | RESERVED | RESERVED | ||
R/W-00b | R/W-00b | R/W-0b | R-0b | R-0b | R-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | ASI_MIX_SEL[1:0] | R/W | 00b | ASI input (from GPIx or GPIO) mixing selection with channel data.
0d = No mixing 1d = Channel 1 and channel 2 output data mixed with ASI input data on channel 1 (slot 0) 2d = Channel 1 and channel 2 output data mixed with ASI input data on channel 2 (slot 1) 3d = Mixed both channel data with ASI input data independently. Mixed asi_in_ch_1 with channel 1 output data and similarly mix asi_in_ch_2 with channel 2 output data |
5-4 | ASI_GAIN_SEL[1:0] | R/W | 00b | ASI input data gain selection before mixing to channel data.
0d = No gain 1d = Gain asi input data by -6dB 2d = Gain asi input data by -12dB 3d = Gain asi input data by -18dB |
3 | ASI_IN_INVERSE | R/W | 0b | Invert ASI input data before mixing to channel data.
0d = No inversion done for ASI input data 1d = ASI input data inverted before mixing with channel data |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
ASI_CH1 is shown in Figure 8-79 and described in Table 8-60.
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This register is the ASI slot configuration register for channel 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_SLOT[5:0] | ||||||
R-00b | R/W-000000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved bits; Write only reset value |
5-0 | CH1_SLOT[5:0] | R/W | 000000b | Channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is left slot 31 32d = TDM is slot 32 or I2S, LJ is right slot 0 33d = TDM is slot 33 or I2S, LJ is right slot 1 34d to 62d = Slot assigned as per configuration 63d = TDM is slot 63 or I2S, LJ is right slot 31 |
ASI_CH2 is shown in Figure 8-80 and described in Table 8-61.
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This register is the ASI slot configuration register for channel 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH2_SLOT[5:0] | ||||||
R-00b | R/W-000001b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved bits; Write only reset value |
5-0 | CH2_SLOT[5:0] | R/W | 000001b | Channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is left slot 31 32d = TDM is slot 32 or I2S, LJ is right slot 0 33d = TDM is slot 33 or I2S, LJ is right slot 1 34d to 62d = Slot assigned as per configuration 63d = TDM is slot 63 or I2S, LJ is right slot 31 |
ASI_CH3 is shown in Figure 8-81 and described in Table 8-62.
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This register is the ASI slot configuration register for channel 3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH3_SLOT[5:0] | ||||||
R-00b | R/W-000010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved bits; Write only reset value |
5-0 | CH3_SLOT[5:0] | R/W | 000010b | Channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is left slot 31 32d = TDM is slot 32 or I2S, LJ is right slot 0 33d = TDM is slot 33 or I2S, LJ is right slot 1 34d to 62d = Slot assigned as per configuration 63d = TDM is slot 63 or I2S, LJ is right slot 31 |
ASI_CH4 is shown in Figure 8-82 and described in Table 8-63.
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This register is the ASI slot configuration register for channel 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH4_SLOT[5:0] | ||||||
R-00b | R/W-000011b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved bits; Write only reset value |
5-0 | CH4_SLOT[5:0] | R/W | 000011b | Channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is left slot 31 32d = TDM is slot 32 or I2S, LJ is right slot 0 33d = TDM is slot 33 or I2S, LJ is right slot 1 34d to 62d = Slot assigned as per configuration 63d = TDM is slot 63 or I2S, LJ is right slot 31 |
MST_CFG0 is shown in Figure 8-83 and described in Table 8-64.
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This register is the ASI master mode configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MST_SLV_CFG | AUTO_CLK_CFG | AUTO_MODE_PLL_DIS | BCLK_FSYNC_GATE | FS_MODE | MCLK_FREQ_SEL[2:0] | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-010b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MST_SLV_CFG | R/W | 0b | ASI master or slave configuration register setting.
0d = Device is in slave mode (both BCLK and FSYNC are inputs to the device) 1d = Device is in master mode (both BCLK and FSYNC are generated from the device) |
6 | AUTO_CLK_CFG | R/W | 0b | Automatic clock configuration setting.
0d = Auto clock configuration is enabled (all internal clock divider and PLL configurations are auto derived) 1d = Auto clock configuration is disabled (custom mode and device GUI must be used for the device configuration settings) |
5 | AUTO_MODE_PLL_DIS | R/W | 0b | Automatic mode PLL setting.
0d = PLL is enabled in auto clock configuration 1d = PLL is disabled in auto clock configuration |
4 | BCLK_FSYNC_GATE | R/W | 0b | BCLK and FSYNC clock gate (valid when the device is in master mode).
0d = Do not gate BCLK and FSYNC 1d = Force gate BCLK and FSYNC when being transmitted from the device in master mode |
3 | FS_MODE | R/W | 0b | Sample rate setting (valid when the device is in master mode).
0d = fS is a multiple (or submultiple) of 48 kHz 1d = fS is a multiple (or submultiple) of 44.1 kHz |
2-0 | MCLK_FREQ_SEL[2:0] | R/W | 010b | These bits select the MCLK (GPIO or GPIx) frequency for the PLL source clock input (valid when the device is in master mode and MCLK_FREQ_SEL_MODE = 0).
0d = 12 MHz 1d = 12.288 MHz 2d = 13 MHz 3d = 16 MHz 4d = 19.2 MHz 5d = 19.68 MHz 6d = 24 MHz 7d = 24.576 MHz |
MST_CFG1 is shown in Figure 8-84 and described in Table 8-65.
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This register is the ASI master mode configuration register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FS_RATE[3:0] | FS_BCLK_RATIO[3:0] | ||||||
R/W-0100b | R/W-1000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | FS_RATE[3:0] | R/W | 0100b | Programmed sample rate of the ASI bus (not used when the device is configured in slave mode auto clock configuration).
0d = 7.35 kHz or 8 kHz 1d = 14.7 kHz or 16 kHz 2d = 22.05 kHz or 24 kHz 3d = 29.4 kHz or 32 kHz 4d = 44.1 kHz or 48 kHz 5d = 88.2 kHz or 96 kHz 6d = 176.4 kHz or 192 kHz 7d = 352.8 kHz or 384 kHz 8d = 705.6 kHz or 768 kHz 9d to 15d = Reserved; Don't use |
3-0 | FS_BCLK_RATIO[3:0] | R/W | 1000b | Programmed BCLK to FSYNC frequency ratio of the ASI bus (not used when the device is configured in slave mode auto clock configuration).
0d = Ratio of 16 1d = Ratio of 24 2d = Ratio of 32 3d = Ratio of 48 4d = Ratio of 64 5d = Ratio of 96 6d = Ratio of 128 7d = Ratio of 192 8d = Ratio of 256 9d = Ratio of 384 10d = Ratio of 512 11d = Ratio of 1024 12d = Ratio of 2048 13d to 15d = Reserved; Don't use |
ASI_STS is shown in Figure 8-85 and described in Table 8-66.
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This register s the ASI bus clock monitor status register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FS_RATE_STS[3:0] | FS_RATIO_STS[3:0] | ||||||
R-1111b | R-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | FS_RATE_STS[3:0] | R | 1111b | Detected sample rate of the ASI bus.
0d = 7.35 kHz or 8 kHz 1d = 14.7 kHz or 16 kHz 2d = 22.05 kHz or 24 kHz 3d = 29.4 kHz or 32 kHz 4d = 44.1 kHz or 48 kHz 5d = 88.2 kHz or 96 kHz 6d = 176.4 kHz or 192 kHz 7d = 352.8 kHz or 384 kHz 8d = 705.6 kHz or 768 kHz 9d to 14d = Reserved status 15d = Invalid sample rate |
3-0 | FS_RATIO_STS[3:0] | R | 1111b | Detected BCLK to FSYNC frequency ratio of the ASI bus.
0d = Ratio of 16 1d = Ratio of 24 2d = Ratio of 32 3d = Ratio of 48 4d = Ratio of 64 5d = Ratio of 96 6d = Ratio of 128 7d = Ratio of 192 8d = Ratio of 256 9d = Ratio of 384 10d = Ratio of 512 11d = Ratio of 1024 12d = Ratio of 2048 13d to 14d = Reserved status 15d = Invalid ratio |
CLK_SRC is shown in Figure 8-86 and described in Table 8-67.
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This register is the clock source configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_PLL_SLV_CLK_SRC | MCLK_FREQ_SEL_MODE | MCLK_RATIO_SEL[2:0] | RESERVED | INV_BCLK_FOR_FSYNC | RESERVED | ||
R/W-0b | R/W-0b | R/W-010b | R/W-0b | R/W-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIS_PLL_SLV_CLK_SRC | R/W | 0b | Audio root clock source setting when the device is configured with the PLL disabled in the auto clock configuration for slave mode (AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source 1d = MCLK (GPIO or GPIx) is used as the audio root clock source (the MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting) |
6 | MCLK_FREQ_SEL_MODE | R/W | 0b | Master mode MCLK (GPIO or GPIx) frequency selection mode (valid when the device is in auto clock configuration).
0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19) configuration 1d = MCLK frequency is specified as a multiple of FSYNC in the MCLK_RATIO_SEL (P0_R22) configuration |
5-3 | MCLK_RATIO_SEL[2:0] | R/W | 010b | These bits select the MCLK (GPIO or GPIx) to FSYNC ratio for master mode or when MCLK is used as the audio root clock source in slave mode.
0d = Ratio of 64 1d = Ratio of 256 2d = Ratio of 384 3d = Ratio of 512 4d = Ratio of 768 5d = Ratio of 1024 6d = Ratio of 1536 7d = Ratio of 2304 |
2 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
1 | INV_BCLK_FOR_FSYNC | R/W | 0b | Invert BCLK polarity only for FSYNC generation in master mode configuration.
0d = Do not invert BCLK polarity for FSYNC generation 1d = Invert BCLK polarity for FSYNC generation |
0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
PDMCLK_CFG is shown in Figure 8-87 and described in Table 8-68.
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This register is the PDM clock generation configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | PDMCLK_DIV[1:0] | |||||
R/W-0b | R/W-10000b | R/W-00b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
6-2 | RESERVED | R/W | 10000b | Reserved bits; Write only reset values |
1-0 | PDMCLK_DIV[1:0] | R/W | 00b | PDMCLK divider value.
0d = PDMCLK is 2.8224 MHz or 3.072 MHz 1d = PDMCLK is 1.4112 MHz or 1.536 MHz 2d = PDMCLK is 705.6 kHz or 768 kHz 3d = PDMCLK is 5.6448 MHz or 6.144 MHz (applicable only for PDM channel 1 and 2) |
PDMIN_CFG is shown in Figure 8-88 and described in Table 8-69.
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This register is the PDM DINx sampling edge configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDMDIN1_EDGE | RESERVED | RESERVED | |||||
R/W-0b | R/W-0b | R-000000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PDMDIN1_EDGE | R/W | 0b | PDMCLK latching edge used for channel 1 and channel 2 data.
0d = Channel 1 data are latched on the negative edge, channel 2 data are latched on the positive edge 1d = Channel 1 data are latched on the positive edge, channel 2 data are latched on the negative edge |
6 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
5-0 | RESERVED | R | 000000b | Reserved bits; Write only reset value |
GPIO_CFG0 is shown in Figure 8-89 and described in Table 8-70.
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This register is the GPIO configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO1_CFG[3:0] | RESERVED | GPIO1_DRV[2:0] | |||||
R/W-0010b | R-0b | R/W-010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | GPIO1_CFG[3:0] | R/W | 0010b | GPIO1 configuration.
0d = GPIO1 is disabled 1d = GPIO1 is configured as a general-purpose output (GPO) 2d = GPIO1 is configured as a device interrupt output (IRQ) 3d = Reserved; Don't use 4d = GPIO1 is configured as a PDM clock output (PDMCLK) 5d = Reserved; Don't use 6d = Reserved; Don't use 7d = PD all ADC channels 8d = GPIO1 is configured as an input to control when MICBIAS turns on or off (MICBIAS_EN) 9d = GPIO1 is configured as a general-purpose input (GPI) 10d = GPIO1 is configured as a master clock input (MCLK) 11d = GPIO1 is configured as an ASI input for daisy-chain or ASI input for mixing (SDIN) 12d = GPIO1 is configured as a PDM data input for channel 1 and channel 2 (PDMDIN1) 13d = GPIO1 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2) 14d to 15d = Reserved; Don't use |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2-0 | GPIO1_DRV[2:0] | R/W | 010b | GPIO1 output drive configuration.
0d = Hi-Z output 1d = Drive active low and active high 2d = Drive active low and weak high 3d = Drive active low and Hi-Z 4d = Drive weak low and active high 5d = Drive Hi-Z and active high 6d to 7d = Reserved; Don't use |
GPO_CFG0 is shown in Figure 8-90 and described in Table 8-71.
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This registeris the GPO configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPO1_CFG[3:0] | RESERVED | GPO1_DRV[2:0] | |||||
R/W-0000b | R-0b | R/W-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | GPO1_CFG[3:0] | R/W | 0000b | IN2M_GPO1 (GPO1) configuration.
0d = GPO1 is disabled 1d = GPO1 is configured as a general-purpose output (GPO) 2d = GPO1 is configured as a device interrupt output (IRQ) 3d = Reserved; Don't use 4d = GPO1 is configured as a PDM clock output (PDMCLK) 5d to 15d = Reserved; Don't use |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2-0 | GPO1_DRV[2:0] | R/W | 000b | IN2M_GPO1 (GPO1) output drive configuration.
0d = Hi-Z output 1d = Drive active low and active high 2d = Reserved; Don't use 3d = Drive active low and Hi-Z 4d = Reserved; Don't use 5d = Drive Hi-Z and active high 6d to 7d = Reserved; Don't use |
GPO_VAL is shown in Figure 8-91 and described in Table 8-72.
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This register is the GPIO and GPO output value register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO1_VAL | GPO1_VAL | RESERVED | |||||
R/W-0b | R/W-0b | R-000000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GPIO1_VAL | R/W | 0b | GPIO1 output value when configured as a GPO.
0d = Drive the output with a value of 0 1d = Drive the output with a value of 1 |
6 | GPO1_VAL | R/W | 0b | GPO1 output value when configured as a GPO.
0d = Drive the output with a value of 0 1d = Drive the output with a value of 1 |
5-0 | RESERVED | R | 000000b | Reserved bits; Write only reset value |
GPIO_MON is shown in Figure 8-92 and described in Table 8-73.
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This register is the GPIO monitor value register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO1_MON | RESERVED | ||||||
R-0b | R-0000000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GPIO1_MON | R | 0b | GPIO1 monitor value when configured as a GPI.
0d = Input monitor value 0 1d = Input monitor value 1 |
6-0 | RESERVED | R | 0000000b | Reserved bits; Write only reset value |
GPI_CFG0 is shown in Figure 8-93 and described in Table 8-74.
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This register is the GPI configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPI1_CFG[2:0] | RESERVED | GPI2_CFG[2:0] | ||||
R-0b | R/W-000b | R-0b | R/W-000b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0b | Reserved bit; Write only reset value |
6-4 | GPI1_CFG[2:0] | R/W | 000b | IN2P_GPI1 (GPI1) configuration.
0d = GPI1 is disabled 1d = GPI1 is configured as a general-purpose input (GPI) 2d = GPI1 is configured as a master clock input (MCLK) 3d = GPI1 is configured as an ASI input for daisy-chain or ASI input for mixing (SDIN) 4d = GPI1 is configured as a PDM data input for channel 1 and channel 2 (PDMDIN1) 5d = GPI1 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2) 6d = Reserved; Don't use 7d = PD all ADC channels |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2-0 | GPI2_CFG[2:0] | R/W | 000b | MICBIAS as GPI2 configuration.
0d = GPI2 is disabled 1d = GPI2 is configured as a general-purpose input (GPI) 2d = GPI2 is configured as a master clock input (MCLK) 3d = GPI2 is configured as an ASI input for daisy-chain or ASI input for mixing (SDIN) 4d = GPI2 is configured as a PDM data input for channel 1 and channel 2 (PDMDIN1) 5d = GPI2 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2) 6d = Reserved; Don't use 7d = PD all ADC channels |
GPI_MON is shown in Figure 8-94 and described in Table 8-75.
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This regiser is the GPI monitor value register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPI1_MON | GPI2_MON | RESERVED | |||||
R-0b | R-0b | R-000000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GPI1_MON | R | 0b | GPI1 monitor value when configured as a GPI.
0d = Input monitor value 0 1d = Input monitor value 1 |
6 | GPI2_MON | R | 0b | GPI2 monitor value when MICBIAS is configured as a GPI.
0d = Input monitor value 0 1d = Input monitor value 1 |
5-0 | RESERVED | R | 000000b | Reserved bits; Write only reset value |
INT_CFG is shown in Figure 8-95 and described in Table 8-76.
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This regiser is the interrupt configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_POL | INT_EVENT[1:0] | RESERVED | LTCH_READ_CFG | RESERVED | |||
R/W-0b | R/W-00b | R-00b | R/W-0b | R-00b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_POL | R/W | 0b | Interrupt polarity.
0d = Active low (IRQZ) 1d = Active high (IRQ) |
6-5 | INT_EVENT[1:0] | R/W | 00b | Interrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event Dont use 2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any unmasked latched interrupts event 3d = INT asserts for 2 ms (typical) one time on each pulse for any unmasked interrupts event |
4-3 | RESERVED | R | 00b | Reserved bits; Write only reset value |
2 | LTCH_READ_CFG | R/W | 0b | Interrupt latch registers readback configuration.
0d = All interrupts can be read through the LTCH registers 1d = Only unmasked interrupts can be read through the LTCH registers |
1-0 | RESERVED | R | 00b | Reserved bits; Write only reset value |
INT_MASK0 is shown in Figure 8-96 and described in Table 8-77.
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This register is the interrupt masks register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK0 | INT_MASK0 | INT_MASK0 | INT_MASK0 | INT_MASK0 | RESERVED | RESERVED | RESERVED |
R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_MASK0 | R/W | 1b | ASI clock error mask.
0d = Do not mask 1d = Mask |
6 | INT_MASK0 | R/W | 1b | PLL Lock interrupt mask.
0d = Do not mask 1d = Mask |
5 | INT_MASK0 | R/W | 1b | ASI input mixing saturation alert mask.
0d = Do not mask 1d = Mask |
4 | INT_MASK0 | R/W | 1b | VAD Power up detect interrupt mask.
0d = Do not mask 1d = Mask |
3 | INT_MASK0 | R/W | 1b | VAD Power down detect interrupt mask.
0d = Do not mask 1d = Mask |
2 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
1 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
0 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
INT_LTCH0 is shown in Figure 8-97 and described in Table 8-78.
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This register is the latched Interrupt readback register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LTCH0 | INT_LTCH0 | INT_LTCH0 | INT_LTCH0 | INT_LTCH0 | RESERVED | RESERVED | RESERVED |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LTCH0 | R | 0b | Interrupt caused by an ASI bus clock error (self-clearing bit).
0d = No interrupt 1d = Interrupt |
6 | INT_LTCH0 | R | 0b | Interrupt caused by PLL LOCK (self-clearing bit).
0d = No interrupt 1d = Interrupt |
5 | INT_LTCH0 | R | 0b | Interrupt caused by ASI input mixing channel saturation alert (self clearing bit).
0d = No interrupt 1d = Interrupt |
4 | INT_LTCH0 | R | 0b | Interrupt caused by VAD power up detect (self clearing bit).
0d = No interrupt 1d = Interrupt |
3 | INT_LTCH0 | R | 0b | Interrupt caused by VAD power down detect (self clearing bit).
0d = No interrupt 1d = Interrupt |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CM_TOL_CFG is shown in Figure 8-98 and described in Table 8-79.
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This register is the ADC common mode configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_INP_CM_TOL_CFG[1:0] | CH2_INP_CM_TOL_CFG[1:0] | RESERVED | |||||
R/W-00b | R/W-00b | R-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | CH1_INP_CM_TOL_CFG[1:0] | R/W | 00b | Channel 1 input common mode variance tolerance configuration.
0d = Common mode variance tolerance for AC coupled = 100 mVpp and DC coupled = 2.82 Vpp 1d = Common Mode Tolerance of: AC/DC Coupled Input=1V peak to peak 2d = Common Mode Tolerance of: AC/DC Coupled Input=0-AVDD(Supported only with Input Impendance of 10 kΩ/20 kΩ). For input impedance of 2.5 kΩ, input common mode tolerance= 0.4V to 2.6V. 3d = Reserved; Don't use |
5-4 | CH2_INP_CM_TOL_CFG[1:0] | R/W | 00b | Channel 2 input common mode variance tolerance configuration.
0d = Common mode variance tolerance for AC coupled = 100 mVpp and DC coupled = 2.82 Vpp 1d = Common Mode Tolerance of: AC/DC Coupled Input=1V peak to peak 2d = Common Mode Tolerance of: AC/DC Coupled Input=0-AVDD(Supported only with Input Impendance of 10 kΩ/20 kΩ). For input impedance of 2.5 kΩ, input common mode tolerance= 0.4V to 2.6V. 3d = Reserved; Don't use |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
BIAS_CFG is shown in Figure 8-99 and described in Table 8-80.
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This register is the bias and ADC configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MBIAS_VAL[2:0] | RESERVED | ADC_FSCALE[1:0] | ||||
R-0b | R/W-000b | R-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0b | Reserved bit; Write only reset value |
6-4 | MBIAS_VAL[2:0] | R/W | 000b | MICBIAS value.
0d = Microphone bias is set to VREF (2.750 V, 2.500 V, or 1.375 V) 1d = Microphone bias is set to VREF x 1.096 (3.014 V, 2.740 V, or 1.507 V) 2d = Microphone bias is set to VCM = IN1M, for ADC single-ended configuration 3d = Microphone bias is set to VCM = IN2M, for ADC single-ended configuration 4d = Microphone bias is set to VCM = average of IN1M and IN2M, for ADC single-ended configuration 5d = Microphone bias is set to VCM = internal crude common mode 6d = Microphone bias is set to AVDD 7d = MICBIAS configured as GPI2 |
3-2 | RESERVED | R | 00b | Reserved bits; Write only reset value |
1-0 | ADC_FSCALE[1:0] | R/W | 00b | ADC full-scale setting (configure this setting based on the AVDD supply minimum voltage used).
0d = VREF is set to 2.75 V to support 2 VRMS for the differential input or 1 VRMS for the single-ended input 1d = VREF is set to 2.5 V to support 1.818 VRMS for the differential input or 0.909 VRMS for the single-ended input 2d = VREF is set to 1.375 V to support 1 VRMS for the differential input or 0.5 VRMS for the single-ended input 3d = Reserved; Don't use |
CH1_CFG0 is shown in Figure 8-100 and described in Table 8-81.
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This register is configuration register 0 for channel 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_INTYP | CH1_INSRC[1:0] | CH1_DC | CH1_IMP[1:0] | RESERVED | CH1_AGCEN | ||
R/W-0b | R/W-00b | R/W-0b | R/W-00b | R-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH1_INTYP | R/W | 0b | Channel 1 input type.
0d = Microphone input 1d = Line input |
6-5 | CH1_INSRC[1:0] | R/W | 00b | Channel 1 input configuration.
0d = Analog differential input 1d = Analog single-ended input 2d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN1 and PDMCLK) 3d = Reserved; Don't use |
4 | CH1_DC | R/W | 0b | Channel 1 input coupling (applicable for the analog input).
0d = AC-coupled input 1d = DC-coupled input |
3-2 | CH1_IMP[1:0] | R/W | 00b | Channel 1 input impedance (applicable for the analog input).
0d = Typical 2.5-kΩ input impedance 1d = Typical 10-kΩ input impedance 2d = Typical 20-kΩ input impedance 3d = Reserved; Don't use |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | CH1_AGCEN | R/W | 0b | Channel 1 automatic gain controller (AGC) setting.
0d = AGC disabled 1d = AGC enabled based on the configuration of bit 3 in register 108 (P0_R108) |
CH1_CFG1 is shown in Figure 8-101 and described in Table 8-82.
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This register is configuration register 1 for channel 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_GAIN[6:0] | CH1_GAIN_SIGN_BIT | ||||||
R/W-0000000b | R/W-0b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | CH1_GAIN[6:0] | R/W | 0000000b | Channel 1 gain.
0d = Channel gain is set to 0 dB 1d = Channel gain is set to 0.5 dB 2d = Channel gain is set to 1 dB 3d to 83d = Channel gain is set as per configuration 84d = Channel gain is set to 42 dB 85d to 127d = Reserved; Don't use |
0 | CH1_GAIN_SIGN_BIT | R/W | 0b | Channel-1 gain sign configuration.
0d = Positive channel gain 1d = Negative channel gain (minimum channel gain supported till -11 dB; supported only for channel input impedance of 10-kΩ and 20-kΩ) |
CH1_CFG2 is shown in Figure 8-102 and described in Table 8-83.
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This register is configuration register 2 for channel 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_DVOL[7:0] | |||||||
R/W-11001001b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH1_DVOL[7:0] | R/W | 11001001b | Channel 1 digital volume control.
0d = Digital volume is muted 1d = Digital volume control is set to -100 dB 2d = Digital volume control is set to -99.5 dB 3d to 200d = Digital volume control is set as per configuration 201d = Digital volume control is set to 0 dB 202d = Digital volume control is set to 0.5 dB 203d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 26.5 dB 255d = Digital volume control is set to 27 dB |
CH1_CFG3 is shown in Figure 8-103 and described in Table 8-84.
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This register is configuration register 3 for channel 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_GCAL[3:0] | RESERVED | ||||||
R/W-1000b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CH1_GCAL[3:0] | R/W | 1000b | Channel 1 gain calibration.
0d = Gain calibration is set to -0.8 dB 1d = Gain calibration is set to -0.7 dB 2d = Gain calibration is set to -0.6 dB 3d to 7d = Gain calibration is set as per configuration 8d = Gain calibration is set to 0 dB 9d = Gain calibration is set to 0.1 dB 10d to 13d = Gain calibration is set as per configuration 14d = Gain calibration is set to 0.6 dB 15d = Gain calibration is set to 0.7 dB |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
CH1_CFG4 is shown in Figure 8-104 and described in Table 8-85.
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This register is configuration register 4 for channel 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_PCAL[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH1_PCAL[7:0] | R/W | 00000000b | Channel 1 phase calibration with modulator clock resolution.
0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 254d = Phase calibration delay as per configuration 255d = Phase calibration delay is set to 255 cycles of the modulator clock |
CH2_CFG0 is shown in Figure 8-105 and described in Table 8-86.
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This register is configuration register 0 for channel 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2_INTYP | CH2_INSRC[1:0] | CH2_DC | CH2_IMP[1:0] | RESERVED | CH2_AGCEN | ||
R/W-0b | R/W-00b | R/W-0b | R/W-00b | R-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH2_INTYP | R/W | 0b | Channel 2 input type.
0d = Microphone input 1d = Line input |
6-5 | CH2_INSRC[1:0] | R/W | 00b | Channel 2 input configuration.
0d = Analog differential input (the GPI1 and GPO1 pin functions must be disabled) 1d = Analog single-ended input (the GPI1 and GPO1 pin functions must be disabled) 2d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN1 and PDMCLK) 3d = Reserved; Don't use |
4 | CH2_DC | R/W | 0b | Channel 2 input coupling (applicable for the analog input).
0d = AC-coupled input 1d = DC-coupled input |
3-2 | CH2_IMP[1:0] | R/W | 00b | Channel 2 input impedance (applicable for the analog input).
0d = Typical 2.5-kΩ input impedance 1d = Typical 10-kΩ input impedance 2d = Typical 20-kΩ input impedance 3d = Reserved; Don't use |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | CH2_AGCEN | R/W | 0b | Channel 2 automatic gain controller (AGC) setting.
0d = AGC disabled 1d = AGC enabled based on the configuration of bit 3 in register 108 (P0_R108) |
CH2_CFG1 is shown in Figure 8-106 and described in Table 8-87.
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This register is configuration register 1 for channel 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2_GAIN[6:0] | CH2_GAIN_SIGN_BIT | ||||||
R/W-0000000b | R/W-0b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | CH2_GAIN[6:0] | R/W | 0000000b | Channel 2 gain.
0d = Channel gain is set to 0 dB 1d = Channel gain is set to 0.5 dB 2d = Channel gain is set to 1 dB 3d to 83d = Channel gain is set as per configuration 84d = Channel gain is set to 42 dB 85d to 127d = Reserved; Don't use |
0 | CH2_GAIN_SIGN_BIT | R/W | 0b | Channel-2 gain sign configuration.
0d = Positive channel gain 1d = Negative channel gain (minimum channel gain supported till -11 dB; supported only for channel input impedance of 10-kΩ and 20-kΩ) |
CH2_CFG2 is shown in Figure 8-107 and described in Table 8-88.
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This register is configuration register 2 for channel 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2_DVOL[7:0] | |||||||
R/W-11001001b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH2_DVOL[7:0] | R/W | 11001001b | Channel 2 digital volume control.
0d = Digital volume is muted 1d = Digital volume control is set to -100 dB 2d = Digital volume control is set to -99.5 dB 3d to 200d = Digital volume control is set as per configuration 201d = Digital volume control is set to 0 dB 202d = Digital volume control is set to 0.5 dB 203d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 26.5 dB 255d = Digital volume control is set to 27 dB |
CH2_CFG3 is shown in Figure 8-108 and described in Table 8-89.
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This register is configuration register 3 for channel 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2_GCAL[3:0] | RESERVED | ||||||
R/W-1000b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CH2_GCAL[3:0] | R/W | 1000b | Channel 2 gain calibration.
0d = Gain calibration is set to -0.8 dB 1d = Gain calibration is set to -0.7 dB 2d = Gain calibration is set to -0.6 dB 3d to 7d = Gain calibration is set as per configuration 8d = Gain calibration is set to 0 dB 9d = Gain calibration is set to 0.1 dB 10d to 13d = Gain calibration is set as per configuration 14d = Gain calibration is set to 0.6 dB 15d = Gain calibration is set to 0.7 dB |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
CH2_CFG4 is shown in Figure 8-109 and described in Table 8-90.
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This register is configuration register 4 for channel 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2_PCAL[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH2_PCAL[7:0] | R/W | 00000000b | Channel 2 phase calibration with modulator clock resolution.
0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 254d = Phase calibration delay as per configuration 255d = Phase calibration delay is set to 255 cycles of the modulator clock |
CH3_CFG2 is shown in Figure 8-110 and described in Table 8-91.
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This register is configuration register 2 for channel 3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3_DVOL[7:0] | |||||||
R/W-11001001b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH3_DVOL[7:0] | R/W | 11001001b | Channel 3 digital volume control.
0d = Digital volume is muted 1d = Digital volume control is set to -100 dB 2d = Digital volume control is set to -99.5 dB 3d to 200d = Digital volume control is set as per configuration 201d = Digital volume control is set to 0 dB 202d = Digital volume control is set to 0.5 dB 203d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 26.5 dB 255d = Digital volume control is set to 27 dB |
CH3_CFG3 is shown in Figure 8-111 and described in Table 8-92.
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This register is configuration register 3 for channel 3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3_GCAL[3:0] | RESERVED | ||||||
R/W-1000b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CH3_GCAL[3:0] | R/W | 1000b | Channel 3 gain calibration.
0d = Gain calibration is set to -0.8 dB 1d = Gain calibration is set to -0.7 dB 2d = Gain calibration is set to -0.6 dB 3d to 7d = Gain calibration is set as per configuration 8d = Gain calibration is set to 0 dB 9d = Gain calibration is set to 0.1 dB 10d to 13d = Gain calibration is set as per configuration 14d = Gain calibration is set to 0.6 dB 15d = Gain calibration is set to 0.7 dB |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
CH3_CFG4 is shown in Figure 8-112 and described in Table 8-93.
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This register is configuration register 4 for channel 3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3_PCAL[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH3_PCAL[7:0] | R/W | 00000000b | Channel 3 phase calibration with modulator clock resolution.
0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 254d = Phase calibration delay as per configuration 255d = Phase calibration delay is set to 255 cycles of the modulator clock |
CH4_CFG2 is shown in Figure 8-113 and described in Table 8-94.
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This register is configuration register 2 for channel 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH4_DVOL[7:0] | |||||||
R/W-11001001b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH4_DVOL[7:0] | R/W | 11001001b | Channel 4 digital volume control.
0d = Digital volume is muted 1d = Digital volume control is set to -100 dB 2d = Digital volume control is set to -99.5 dB 3d to 200d = Digital volume control is set as per configuration 201d = Digital volume control is set to 0 dB 202d = Digital volume control is set to 0.5 dB 203d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 26.5 dB 255d = Digital volume control is set to 27 dB |
CH4_CFG3 is shown in Figure 8-114 and described in Table 8-95.
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This register is configuration register 3 for channel 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH4_GCAL[3:0] | RESERVED | ||||||
R/W-1000b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CH4_GCAL[3:0] | R/W | 1000b | Channel 4 gain calibration.
0d = Gain calibration is set to -0.8 dB 1d = Gain calibration is set to -0.7 dB 2d = Gain calibration is set to -0.6 dB 3d to 7d = Gain calibration is set as per configuration 8d = Gain calibration is set to 0 dB 9d = Gain calibration is set to 0.1 dB 10d to 13d = Gain calibration is set as per configuration 14d = Gain calibration is set to 0.6 dB 15d = Gain calibration is set to 0.7 dB |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
CH4_CFG4 is shown in Figure 8-115 and described in Table 8-96.
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This register is configuration register 4 for channel 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH4_PCAL[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH4_PCAL[7:0] | R/W | 00000000b | Channel 4 phase calibration with modulator clock resolution.
0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 254d = Phase calibration delay as per configuration 255d = Phase calibration delay is set to 255 cycles of the modulator clock |
DSP_CFG0 is shown in Figure 8-116 and described in Table 8-97.
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This register is the digital signal processor (DSP) configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_DVOL_OTF_CHG | RESERVED | DECI_FILT[1:0] | CH_SUM[1:0] | HPF_SEL[1:0] | |||
R/W-0b | R/W-0b | R/W-00b | R/W-00b | R/W-01b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIS_DVOL_OTF_CHG | R/W | 0b | Disable run-time changes to DVOL settings.
0d = Digital volume control changes supported while ADC is powered-on 1d = Digital volume control changes not supported while ADC is powered-on. This is useful for 384 kHz and higher sample rate if more than one channel processing is required. |
6 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
5-4 | DECI_FILT[1:0] | R/W | 00b | Decimation filter response.
0d = Linear phase 1d = Low latency 2d = Ultra-low latency 3d = Reserved; Don't use |
3-2 | CH_SUM[1:0] | R/W | 00b | Channel summation mode for higher SNR
0d = Channel summation mode is disabled 1d = 2-channel summation mode is enabled to generate a (CH1 + CH2) / 2 output 2d = Reserved; Don't use 3d = Reserved; Don't use |
1-0 | HPF_SEL[1:0] | R/W | 01b | High-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default coefficient values in P4_R72 to P4_R83 set as the all-pass filter 1d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is selected 2d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected 3d = HPF with a cutoff of 0.008 x fS (384 Hz at fS = 48 kHz) is selected |
DSP_CFG1 is shown in Figure 8-117 and described in Table 8-98.
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This register is the digital signal processor (DSP) configuration register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DVOL_GANG | BIQUAD_CFG[1:0] | DISABLE_SOFT_STEP | AGC_SEL | RESERVED | RESERVED | EN_AVOID_CLIP | |
R/W-0b | R/W-10b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DVOL_GANG | R/W | 0b | DVOL control ganged across channels.
0d = Each channel has its own DVOL CTRL settings as programmed in the CHx_DVOL bits 1d = All active channels must use the channel 1 DVOL setting (CH1_DVOL) irrespective of whether channel 1 is turned on or not |
6-5 | BIQUAD_CFG[1:0] | R/W | 10b | Number of biquads per channel configuration.
0d = No biquads per channel; biquads are all disabled 1d = 1 biquad per channel 2d = 2 biquads per channel 3d = 3 biquads per channel |
4 | DISABLE_SOFT_STEP | R/W | 0b | Soft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled 1d = Soft-stepping disabled |
3 | AGC_SEL | R/W | 0b | AGC Selection when is enabled for any channel
0d = AGC is not selected 1d = AGC is selected |
2 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
0 | EN_AVOID_CLIP | R/W | 0b | Anti clippler when channel gain > 0 dB and AGC mode enabled.
0d = Channel gain is maintained as per user programmed value 1d = Signal level is compressed to avoid clipping when channel gain > 0 dB amd signal level crosses programmed threshold setting set in page-4. |
AGC_CFG0 is shown in Figure 8-118 and described in Table 8-99.
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This register is the automatic gain controller (AGC) configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AGC_LVL[3:0] | AGC_MAXGAIN[3:0] | ||||||
R/W-1110b | R/W-0111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | AGC_LVL[3:0] | R/W | 1110b | AGC output signal target level.
0d = Output signal target level is -6 dB 1d = Output signal target level is -8 dB 2d = Output signal target level is -10 dB 3d to 13d = Output signal target level is as per configuration 14d = Output signal target level is -34 dB 15d = Output signal target level is -36 dB |
3-0 | AGC_MAXGAIN[3:0] | R/W | 0111b | AGC maximum gain allowed.
0d = Maximum gain allowed is 3 dB 1d = Maximum gain allowed is 6 dB 2d = Maximum gain allowed is 9 dB 3d to 11d = Maximum gain allowed is as per configuration 12d = Maximum gain allowed is 39 dB 13d = Maximum gain allowed is 42 dB 14d to 15d = Reserved; Don't use |
GAIN_CFG is shown in Figure 8-119 and described in Table 8-100.
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This register is the channel gain change configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OTF_GAIN_CHANGE_CFG[1:0] | RESERVED | RESERVED | |||||
R/W-00b | R/W-0b | R-00000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | OTF_GAIN_CHANGE_CFG[1:0] | R/W | 00b | On the fly channel gain change configuration
0d = On-the-fly gain change with some artifacts due to applying gain change immediately 1d = On-the-fly gain change enabled with reduced artifacts but without soft-stepping 2d = On-the-fly gain change enabled with soft-stepping of 0.5 dB per ~20 µs, supported channel gain up to 30 dB for 10-kΩ input impedance mode and 24 dB for 20-kΩ input impedance mode 3d = On-the-fly gain change enabled with soft-stepping of 0.5 dB per ~40 µs, supported channel gain up to 30 dB for 10-kΩ input impedance mode and 24 dB for 20-kΩ input impedance mode |
5 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
4-0 | RESERVED | R | 00000b | Reserved bits; Write only reset value |
IN_CH_EN is shown in Figure 8-120 and described in Table 8-101.
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This register is the input channel enable configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN_CH1_EN | IN_CH2_EN | IN_CH3_EN | IN_CH4_EN | RESERVED | |||
R/W-1b | R/W-1b | R/W-0b | R/W-0b | R-0000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IN_CH1_EN | R/W | 1b | Input channel 1 enable setting.
0d = Channel 1 is disabled 1d = Channel 1 is enabled |
6 | IN_CH2_EN | R/W | 1b | Input channel 2 enable setting.
0d = Channel 2 is disabled 1d = Channel 2 is enabled |
5 | IN_CH3_EN | R/W | 0b | Input channel 3 (PDM only) enable setting.
0d = Channel 3 is disabled 1d = Channel 3 is enabled |
4 | IN_CH4_EN | R/W | 0b | Input channel 4 (PDM only) enable setting.
0d = Channel 4 is disabled 1d = Channel 4 is enabled |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
ASI_OUT_CH_EN is shown in Figure 8-121 and described in Table 8-102.
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This register is the ASI output channel enable configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASI_OUT_CH1_EN | ASI_OUT_CH2_EN | ASI_OUT_CH3_EN | ASI_OUT_CH4_EN | RESERVED | |||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ASI_OUT_CH1_EN | R/W | 0b | ASI output channel 1 enable setting.
0d = Channel 1 output slot is in a tri-state condition 1d = Channel 1 output slot is enabled |
6 | ASI_OUT_CH2_EN | R/W | 0b | ASI output channel 2 enable setting.
0d = Channel 2 output slot is in a tri-state condition 1d = Channel 2 output slot is enabled |
5 | ASI_OUT_CH3_EN | R/W | 0b | ASI output channel 3 enable setting.
0d = Channel 3 output slot is in a tri-state condition 1d = Channel 3 output slot is enabled |
4 | ASI_OUT_CH4_EN | R/W | 0b | ASI output channel 4 enable setting.
0d = Channel 4 output slot is in a tri-state condition 1d = Channel 4 output slot is enabled |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
PWR_CFG is shown in Figure 8-122 and described in Table 8-103.
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This register is the power-up configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MICBIAS_PDZ | ADC_PDZ | PLL_PDZ | DYN_CH_PUPD_EN | DYN_MAXCH_SEL[1:0] | RESERVED | VAD_EN | |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-00b | R/W-0b | R/W-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MICBIAS_PDZ | R/W | 0b | Power control for MICBIAS.
0d = Power down MICBIAS 1d = Power up MICBIAS |
6 | ADC_PDZ | R/W | 0b | Power control for ADC and PDM channels.
0d = Power down all ADC and PDM channels 1d = Power up all enabled ADC and PDM channels |
5 | PLL_PDZ | R/W | 0b | Power control for the PLL.
0d = Power down the PLL 1d = Power up the PLL |
4 | DYN_CH_PUPD_EN | R/W | 0b | Dynamic channel power-up, power-down enable.
0d = Channel power-up, power-down is not supported if any channel recording is on 1d = Channel can be powered up or down individually, even if channel recording is on |
3-2 | DYN_MAXCH_SEL[1:0] | R/W | 00b | Dynamic mode maximum channel select configuration.
0d = Channel 1 and channel 2 are used with dynamic channel power-up, power-down feature enabled 1d = Channel 1 to channel 4 are used with dynamic channel power-up, power-down feature enabled 2d = Reserved; Don't use 3d = Reserved; Don't use |
1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
0 | VAD_EN | R/W | 0b | Enable voice activity detection (VAD) algorithm.
0d = VAD is disabled 1d = VAD is enabled |
DEV_STS0 is shown in Figure 8-123 and described in Table 8-104.
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This register is the device status value register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_STATUS | CH2_STATUS | RESERVED | |||||
R-0b | R-0b | R-000000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH1_STATUS | R | 0b | ADC or PDM channel 1 power status.
0d = ADC or PDM channel is powered down 1d = ADC or PDM channel is powered up |
6 | CH2_STATUS | R | 0b | ADC or PDM channel 2 power status.
0d = ADC or PDM channel is powered down 1d = ADC or PDM channel is powered up |
5-0 | RESERVED | R | 000000b | Reserved bits; Write only reset value |
DEV_STS1 is shown in Figure 8-124 and described in Table 8-105.
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This register is the device status value register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE_STS[2:0] | RESERVED | ||||||
R-100b | R-00000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | MODE_STS[2:0] | R | 100b | Device mode status.
4d = Device is in sleep mode or software shutdown mode 6d = Device is in active mode with all ADC or PDM channels turned off 7d = Device is in active mode with at least one ADC or PDM channel turned on |
4-0 | RESERVED | R | 00000b | Reserved bits; Write only reset value |
I2C_CKSUM is shown in Figure 8-125 and described in Table 8-106.
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This register returns the I2C transactions checksum value.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2C_CKSUM[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | I2C_CKSUM[7:0] | R/W | 00000000b | These bits return the I2C transactions checksum value. Writing to this register resets the checksum to the written value. This register is updated on writes to other registers on all pages. |