ZHCSMB3A March 2021 – April 2022 TLIN2021A-Q1
PRODMIX
Figure 8-1 Test System: Operating Voltage Range
with RX and TX Access: Parameters 9, 10
Figure 8-2 RX Response: Operating Voltage
Range
Figure 8-3 LIN Bus Input Signal
Figure 8-4 LIN Receiver Test with RX access
Param 17, 18, 19, 20
Figure 8-5 VSUP_NON_OP Param
11
Figure 8-6 Test Circuit for
IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V, Param 13
Figure 8-7 Test Circuit for
IBUS_PAS_rec Param 14
Figure 8-8 Test Circuit Slope Control and Duty
Cycle Param 27, 28, 29, 30
Figure 8-9 Definition of Bus Timing
Parameters
Figure 8-10 Propagation Delay Test Circuit;
Param 31, 32
Figure 8-11 Propagation Delay
Figure 8-12 Mode Transitions
Figure 8-13 Wake-up Through EN
Figure 8-14 Wake-up through LIN