ZHCSE50A
September 2015 – March 2016
TLC59291
PRODUCTION DATA.
1
特性
2
应用范围
3
说明
4
修订历史记录
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Timing Diagrams
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Maximum Constant Sink Current
8.3.2
Global Brightness Control (BC) Function
8.3.3
Thermal Shutdown (TSD) and Thermal Error Flag (TEF)
8.3.4
Pre-Thermal Warning (PTW)
8.3.5
Current Reference Terminal - IREF Terminal - Short Flag (ISF)
8.3.6
Noise Reduction
8.4
Device Functional Modes
8.4.1
Blank Mode Selection (BLKMS)
8.4.2
Power-Save Mode
8.4.3
LED Open Detection (LOD)
8.4.4
LED Short Detection (LSD)
8.4.5
Invisible Detection Mode (IDM)
8.4.6
Output Leakage Detection (OLD)
8.4.7
Status Information Data (SID)
8.5
Register Maps
8.5.1
Register and Data Latch Configuration
8.5.1.1
Common Shift Register
8.5.1.2
Output On/Off Data Latch
8.5.1.3
Control Data Latch
8.5.1.4
Output On/Off Data Write Timing and Output Control
8.5.1.5
Function Control Data Writing
8.5.1.6
Function Control (FC) Data
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
器件和文档支持
12.1
文档支持
12.2
社区资源
12.3
商标
12.4
静电放电警告
12.5
Glossary
13
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RGE|24
MPQF124G
散热焊盘机械数据 (封装 | 引脚)
RGE|24
QFND008AA
订购信息
zhcse50a_oa
11 Layout
11.1 Layout Guidelines
Place the decoupling capacitor near the VCC pin and GND plane
Place the current programming resistor R
IREF
close to the IREF pin an the IREFGND pin.
Route the GND pattern as widely as possible for large GND currents.
The routing wire between the LED cathode side and the device OUTXn pin must be as short and straight as possible to reduce wire inductance.
When several ICs are chained, symmetric placements are recommended.
11.2 Layout Example
Figure 39. Layout