ZHCSH32 November   2017 TLA2021 , TLA2022 , TLA2024

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      系统监控应用示例
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Analog Inputs
      3. 8.3.3 Full-Scale Range (FSR) and LSB Size
      4. 8.3.4 Voltage Reference
      5. 8.3.5 Oscillator
      6. 8.3.6 Output Data Rate and Conversion Time
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset and Power-Up
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Single-Shot Conversion Mode
        2. 8.4.2.2 Continuous-Conversion Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 I2C Address Selection
        2. 8.5.1.2 I2C Interface Speed
        3. 8.5.1.3 Serial Clock (SCL) and Serial Data (SDA)
        4. 8.5.1.4 I2C Data Transfer Protocol
        5. 8.5.1.5 Timeout
        6. 8.5.1.6 I2C General-Call (Software Reset)
      2. 8.5.2 Reading and Writing Register Data
        1. 8.5.2.1 Reading Conversion Data or the Configuration Register
        2. 8.5.2.2 Writing the Configuration Register
      3. 8.5.3 Data Format
  9. 9 Register Maps
    1. 9.1 Conversion Data Register (RP = 00h) [reset = 0000h]
      1. Table 6. Conversion Data Register Field Descriptions
    2. 9.2 Configuration Register (RP = 01h) [reset = 8583h]
      1. Table 7. Configuration Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Basic Interface Connections
      2. 10.1.2 Connecting Multiple Devices
      3. 10.1.3 Single-Ended Signal Measurements
      4. 10.1.4 Analog Input Filtering
      5. 10.1.5 Duty Cycling To Reduce Power Consumption
      6. 10.1.6 I2C Communication Sequence Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +85°C; typical specifications are at TA = 25°C; all specifications are at VDD = 3.3 V, data rate = 128 SPS, and FSR = ±2.048 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Common-mode input impedance FSR = ±6.144 V(1) 10 MΩ
FSR = ±4.096 V(1), FSR = ±2.048 V 6
FSR = ±1.024 V 3
FSR = ±0.512 V, FSR = ±0.256 V 100
Differential input impedance FSR = ±6.144 V(1) 22 MΩ
FSR = ±4.096 V(1) 15
FSR = ±2.048 V 4.9
FSR = ±1.024 V 2.4
FSR = ±0.512 V, ±0.256 V 710 kΩ
SYSTEM PERFORMANCE
Resolution (no missing codes) 12 Bits
DR Data rate 128, 250, 490, 920, 1600, 2400, 3300 SPS
Data rate variation All data rates –10% 10%
INL Integral nonlinearity(2) 1 LSB
Offset error ±1 LSB
Offset drift 0.01 LSB/°C
Gain error(3) 0.05%
Gain drift(3) 10 ppm/°C
PSRR Power-supply rejection ratio 85 dB
CMRR Common-mode rejection ratio 90 dB
DIGITAL INPUT/OUTPUT
VIL Logic input level, low GND 0.3 VDD V
VIH Logic input level, high 0.7 VDD 5.5 V
VOL Logic output level, low IOL = 3 mA GND 0.15 0.4 V
Input leakage current GND < VDigital Input< VDD –10 10 µA
POWER SUPPLY
IVDD Supply current Power-down 0.5 µA
Operating 150
PD Power dissipation VDD = 5 V 0.9 mW
VDD = 3.3 V 0.5
VDD = 2 V 0.3
(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. See the Full-Scale Range (FSR) and LSB Size section for more information.
(2) Best-fit INL; covers 99% of full-scale.
(3) Includes all errors from onboard PGA and voltage reference.