ZHCSKJ6 December   2019 TL16C750E

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     方框图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. 7.1      ESD Ratings
    3. Table 2. Recommended Operating Conditions
    4. Table 3. Thermal Information
    5. Table 4. Electrical Characteristics
    6. Table 5. Timing Requirements
    7. 7.2      Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  UART Modes
      2. 9.3.2  Trigger Levels
      3. 9.3.3  Hardware Flow Control
      4. 9.3.4  Auto-RTS
      5. 9.3.5  Auto-CTS
      6. 9.3.6  Software Flow Control
      7. 9.3.7  Software Flow Control Example
      8. 9.3.8  Reset
      9. 9.3.9  Interrupts
      10. 9.3.10 Interrupt Mode Operation
      11. 9.3.11 Polled Mode Operation
      12. 9.3.12 Break and Timeout Conditions
      13. 9.3.13 Programmable Baud Rate Generator with Fractional Divisor
      14. 9.3.14 Fractional Divisor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Interface Mode
        1. 9.4.1.1 IOR Used (MODE = VCC)
        2. 9.4.1.2 IOR Unused (MODE = GND)
      2. 9.4.2 DMA Signaling
        1. 9.4.2.1 Single DMA Transfers (DMA Mode 0 or FIFO Disable)
        2. 9.4.2.2 Block DMA Transfers (DMA Mode 1)
      3. 9.4.3 Sleep Mode
    5. 9.5 Register Maps
      1. 9.5.1  Registers Operations
      2. 9.5.2  Receiver Holding Register (RHR)
      3. 9.5.3  Transmit Holding Register (THR)
      4. 9.5.4  FIFO Control Register (FCR)
      5. 9.5.5  Line Control Register (LCR)
      6. 9.5.6  Line Status Register (LSR)
      7. 9.5.7  Modem Control Register (MCR)
      8. 9.5.8  Modem Status Register (MSR)
      9. 9.5.9  Interrupt Enable Register (IER)
      10. 9.5.10 Interrupt Identification Register (IIR)
      11. 9.5.11 Enhanced Feature Register (EFR)
      12. 9.5.12 Divisor Latches (DLL, DLH, DLF)
      13. 9.5.13 Transmission Control Register (TCR)
      14. 9.5.14 Trigger Level Register (TLR)
      15. 9.5.15 FIFO Ready Register
      16. 9.5.16 Alternate Function Register (AFR)
      17. 9.5.17 RS-485 Mode
      18. 9.5.18 IrDA Overview
      19. 9.5.19 IrDA Encoder Function
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Set the desired baud rate
        2. 10.2.2.2 Reset the fifos
        3. 10.2.2.3 Sending data on the bus
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.5.16 Alternate Function Register (AFR)

The AFR is used to enable some extra functionality beyond the capabilities of the original TL16C750. The first addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to 115.2 kbps. The third addition is support for RS-485 bus drivers or transceivers by providing an output pin (DTR), which is timed to keep the RS-485 driver enabled as long as transmit data is pending.

The AFR is located at A[2:0] = 010 when LCR[7:5] = 100.

Table 27. AFR Bit Settings

BIT BIT SETTINGS
0 Reserved bit. Does not do anything
1 IREN enables the IrDA SIR mode. This mode is only specified to 115.2 bps; TI does not recommend the use of this mode at higher speeds.
2 485EN enables the half duplex RS-485 mode and causes the DTR output to be set high whenever there is any data in the THR or TSR and to be held high until the delay set by DLY2:0 has expired, at which time it is set low. The DTR output is intended to drive the enabled input of an RS-485 driver. When this bit is set, the transmitter interrupts are held off until the TSR is empty, unless 485LG is set.
3 485LG is set when the 485EN is set. This bit indicates that a relatively large data block is being set, requiring more than a single load of the xmt fifo. In this case, the transmitter interrupts occur as in the standard RS-232 mode, either when the xmt fifo contents drop below the xmt threshold or when the xmt fifo is empty.
4 RCVEN is valid only when 485EN or IREN is set, and allows the serial receiver to listen in or snoop on the RS-485 traffic or IrDA traffic. RS-485 mode is generally considered half duplex, and usually a node is either driving or receiving, but there can be cases when it is advantageous to verify what you are sending. This can be used to detect collisions or as part of an arbitration mechanism on the bus. When both RCVEN and 485EN are set, the receiver stores any data presented on RX, if any. Note that implies that the external RS-485 receiver is enabled. Whenever 485EN is cleared, the serial receiver is enabled for normal full duplex RS-232 traffic. If RCVEN is cleared while 485EN is set, the receiver is disabled while transmitting. SIR is also considered half duplex. Often the light energy from the transmitting LED is coupled back into the receiving PIN diode, which creates an input data stream that is not of interest to the host. Disabling the receiver (clearing RCVEN) prevents this reception, and eliminates the task of unloading the data. On the other hand, for diagnostic or other purposes, it may be useful to observe this data stream. For example, a mirror could be used to intentionally couple the output LED to the input PIN. For these cases, RCVEN could be set to enable the receiver.
NOTE: When RCVEN is cleared (set to 0), the character timeout interrupt is not available, even in RS-232 mode. This can be useful when checking code for valid threshold interrupts, as the timeout interrupt does not override the threshold interrupt.
7:5 DLY2 to DLY0 sets a delay after the last stop bit of the last data byte being set before the DTR is set low, to allow for long cable runs. The delay is in number of bit times and is enabled by 485EN. The delay starts only when both the xmt serial shift register (TSR) is empty and the xmt fifo (THR) is empty, and if started, is cleared by any data being written to the THR.

Table 28. LOOP and RCVEN Functionality

LOOP MODE RCVEN AFR MODE DESCRIPTION
LOOP mode off,
MCR4 = 0,
RX, TX active		 RCVEN = 1 AFR = 10 RS-232 Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 14 RS-485 Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 12 IrDA Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
RCVEN = 0 AFR = 00 RS-232 Receive threshold and error detection interrupts available
Data stored in receive FIFO
AFR = 04 RS-485 No data stored in receive FIFO, hence no interrupts available
AFR = 02 IrDA No data stored in receive FIFO, hence no interrupts available
LOOP mode on,
MCR4 = 1,
RX, TX inactive		 RCVEN = 1 AFR = 10 RS-232 Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 14 RS-485 Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 12 IrDA Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
RCVEN = 0 AFR = 00 RS-232 Receive threshold and error detection interrupts available
Data stored in receive FIFO
AFR = 04 RS-485 Receive threshold and error detection interrupts available
Data stored in receive FIFO
AFR = 02 IrDA Receive threshold and error detection interrupts available
Data stored in receive FIFO