ZHCSGP5C August   2017  – February 2022 TIC12400-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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Continuous Mode

In continuous mode, wetting current is continuously applied to each enabled input channel, and the status of each channel is sampled sequentially (starting from the IN0 to IN23). The TIC12400-Q1 monitors enabled inputs and issues an interrupt (if enabled) if a switch status change event is detected. The wetting current setting for each input can be individually adjusted by configuring the WC_CFG0 and WC_CFG1 to the 0 mA, 1 mA, 2 mA, 5 mA, 10 mA, or 15 mA setting. Each input is monitored by either a comparator or an ADC depending on the setting of the input mode in the register MODE.

Figure 8-11 below illustrates an example of the timing diagram of the detection sequence in continuous mode. After the TRIGGER bit in register CONFIG is set to logic 1, it takes tSTARTUP to activate the wetting current for all enabled inputs. The wetting currents stay on continuously, while each input is routed to the ADC and comparator for sampling in a sequential fashion. After conversion and comparison is done for an input, the switch status (below or above detection threshold) is stored in registers (IN_STAT_COMP for comparator inputs and IN_STAT_ADC0 to IN_STAT_ADC1 for ADC inputs) to be used as the default state for subsequent detection cycles. The digital values (if the input is configured as ADC input mode) are stored in the registers ANA_STAT0 to ANA_STAT11. After the end of the first polling cycle, the INT pin is asserted low to notify the microcontroller that the default switch status is ready to be read. The SSC bit in INT_STAT register and the SPI status flag SSC are also asserted to logic 1. The polling cycle time (tPOLL) determines how frequently each input is sampled and can be configured in the register CONFIG.

GUID-A46E9611-A0EF-4785-94BC-2B4F3B173129-low.gifFigure 8-11 An Example of the Detection Sequence in Continuous Mode

The INT_STAT register is cleared and INT pin de-asserted if a SPI READ command is issued to the register. Note: the interrupt is always generated after the 1st detection cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In subsequent detection cycles, the interrupt is generated only if switch status change is detected.

No wetting currents are applied to 0 mA- configured inputs, although some biasing current (as specified by IIN_LEAK_0mA) may still flow in and out of the input. Threshold crossing monitoring is still performed for the input using one or more of the defined thresholds. The 0 mA setting is useful for the integrated ADC or comparator to measure applied voltage on a specific input without being affected by the device wetting current.