ZHCSOO2B December   2022  – March 2024 THVD2410V , THVD2412V , THVD2450V , THVD2452V

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics_250 kbps
    9. 5.9  Switching Characteristics_1 Mbps
    10. 5.10 Switching Characteristics_20 Mbps
    11. 5.11 Switching Characteristics_50 Mbps
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 ±70 V Fault Protection
      2. 7.3.2 Integrated IEC ESD and EFT Protection
      3. 7.3.3 Driver Overvoltage and Overcurrent Protection
      4. 7.3.4 Enhanced Receiver Noise Immunity
      5. 7.3.5 Receiver Fail-Safe Operation
      6. 7.3.6 Low-Power Shutdown Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Transient Protection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方产品免责声明
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

Figure 4-1 THVD2410V, THVD2450V
10-Pin DRC Package (VSON)
Top View
Table 4-1 Pin Functions
NO. NAME TYPE DESCRIPTION
1 VIO Logic Supply Supply for logic I/O signals (R, RE, D, DE, and SLR)
2 R Digital Output Receive data output
3 DE Digital Input Driver enable input; integrated pull-down
4 RE Digital Input Receiver enable input; integrated pull-up
5 D Digital Input Transmission data input; integrated pull-up
6 GND Reference Potential Local device ground
7 SLR Digital Input Slew rate select. For THVD2410V: Low = 1 Mbps, High = 250 kbps. Defaults to 1 Mbps if SLR is left floating. For THVD2450V: Low = 50 Mbps, High = 20 Mbps. Defaults to 50 Mbps if left floating.
8 A Bus I/O RS 485 bus I/O, A
9 B Bus I/O RS 485 bus I/O, B
10 VCC Bus Supply Bus supply
Thermal Pad -- Connect to GND for optimal thermal performance
GUID-20220314-CA0I-ZQGV-5QMH-76CFVKBFP7FK-low.svg Figure 4-2 THVD2412V, THVD2452V
14-Pin SOIC Package (D)
Top View
Table 4-2 Pin functions
NO. NAME TYPE DESCRIPTION
1 VIO Logic supply 1.65 V to 5.5 V supply for logic I/O signals (R, RE, D, DE and SLR)
2 R Digital output Receive data output
3 RE Digital input Receiver enable input; integrated pull-up
4 DE Digital input Driver enable input; integrated pull-down
5 D Digital input Transmission data input; integrated pull-up
6 GND Reference potential Local device ground
7 NC No connect Not connected internally
8 SLR Digital input Slew rate select. For THVD2412V: Low = 1 Mbps, High = 250 kbps. Defaults to 1 Mbps if SLR is left floating. For THVD2452V: Low = 50 Mbps, High = 20 Mbps. Defaults to 50 Mbps if left floating.
9 Y Bus output RS 485 driver non-inverting output
10 Z Bus output RS 485 driver inverting output
11 B Bus input RS 485 receiver inverting input
12 A Bus input RS 485 receiver non-inverting input
13 NC No connect Not connected internally
14 VCC Bus supply 3 V to 5.5 V bus supply