SLOS616D March   2010  – March 2015 THS788

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Host Serial Interface DC Characteristics
    7. 7.7 Host Serial Interface AC Characteristics
    8. 7.8 Power Consumption
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Counter, Latches, Clock Multiplier
      2. 8.3.2 Channels, Interpolator
      3. 8.3.3 FIFO
      4. 8.3.4 Calibration, ALU, Tag, Shifter
      5. 8.3.5 Serial Interface, Temperature, Overhead
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial-Results Interface
      2. 8.4.2 Result-Interface Clock
      3. 8.4.3 DDR Mode
      4. 8.4.4 Output Interface Throughput
      5. 8.4.5 Counter Range
        1. 8.4.5.1 Preconditioning Holdoff Delay Time
        2. 8.4.5.2 Arming Conditions
      6. 8.4.6 Resister Map Descriptions for All Channels and Central Register
    5. 8.5 Programming
      1. 8.5.1 Host Processor Bus Interface
        1. 8.5.1.1  Serial Interface
        2. 8.5.1.2  Read vs Write Cycle
        3. 8.5.1.3  Parallel (Broadcast) Write
        4. 8.5.1.4  Address
        5. 8.5.1.5  Data
        6. 8.5.1.6  Reset
        7. 8.5.1.7  Chip ID
        8. 8.5.1.8  Read Operations
        9. 8.5.1.9  Write Operations
        10. 8.5.1.10 Write Operations to Multiple Destinations
      2. 8.5.2 Serial-Results Interface and ALU
        1. 8.5.2.1 Event Latches
        2. 8.5.2.2 FIFO
        3. 8.5.2.3 Result-Interface Operation
        4. 8.5.2.4 Serial Results Latency
        5. 8.5.2.5 TMU Calibration
        6. 8.5.2.6 Temperature Sensor
    6. 8.6 Register Maps
      1. 8.6.1 Register Address Space
      2. 8.6.2 Register Map Detail
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 Time Measurement
        2. 9.2.2.2 Output Clock to Data/Strobe Phasing
        3. 9.2.2.3 Master Clock Input and Clock Multiplier
        4. 9.2.2.4 Temperature Measurement and Alarm Circuit
        5. 9.2.2.5 LVDS-Compatible I/Os
        6. 9.2.2.6 LVDS-Compatible Inputs
        7. 9.2.2.7 LVDS-Compatible Outputs
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

PFD Package
100-Pin HTQFP
(Top View)
THS788 P0011-03a_LOS616.gif

NOTE:

Pin 1 indicator is symbolized with a white dot, and is located near pin 1 corner.

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
EventA 68 LVDS-compatible input Positive event input for channel A
EventA 66 LVDS-compatible input Negative event input for channel A
EventB 61 LVDS-compatible input Positive event input for channel B
EventB 63 LVDS-compatible input Negative event input for channel B
EventC 8 LVDS-compatible input Positive event input for channel C
EventC 10 LVDS-compatible input Negative event input for channel C
EventD 15 LVDS-compatible input Positive event input for channel D
EventD 13 LVDS-compatible input Negative event input for channel D
GND 1, 2, 11, 12, 21, 25, 32, 35, 37, 39, 42, 55, 64, 65, 74, 75, 82, 84, 85, 87, 89, 92, 94 Ground Chip ground
HCLK 34 LVCMOS input Host serial-interface clock
Hdata 33 LVCMOS I/O Host serial-interface data I/O
Hstrobe 41 LVCMOS input Host serial-interface chip select
MCLK 19 LVDS-compatible input Positive master-clock input
MCLK 20 LVDS-compatible input Negative master-clock input
NC 3–6, 9, 14, 17, 18, 26, 50, 54, 59, 62, 67, 70–73, 76, 100 No connect Physically not connected to silicon
OT_ALARM 53 Open-drain output Overtemperature alarm
RCLK 45 LVDS-compatible output Positive result-interface clock
RCLK 44 LVDS-compatible output Negative result-interface clock
RdataA 78 LVDS-compatible output Positive result-data output for channel A
RdataA 79 LVDS-compatible output Negative result-data output for channel A
RdataB 49 LVDS-compatible output Positive result-data output for channel B
RdataB 48 LVDS-compatible output Negative result-data output for channel B
RdataC 98 LVDS-compatible output Positive result-data output for channel C
RdataC 97 LVDS-compatible output Negative result-data output for channel C
RdataD 27 LVDS-compatible output Positive result-data output for channel D
RdataD 28 LVDS-compatible output Negative result-data output for channel D
Reserved 23, 24, 90, 91 Engineering or test pins Connect to VCC
Reset 51 LVCMOS input Chip reset, active-low
RstrobeA 80 LVDS-compatible output Positive strobe signal for channel A
RstrobeA 81 LVDS-compatible output Negative strobe signal for channel A
RstrobeB 47 LVDS-compatible output Positive strobe signal for channel B
RstrobeB 46 LVDS-compatible output Negative strobe signal for channel B
RstrobeC 96 LVDS-compatible output Positive strobe signal for channel C
RstrobeC 95 LVDS-compatible output Negative strobe signal for channel C
RstrobeD 29 LVDS-compatible output Positive strobe signal for channel D
RstrobeD 30 LVDS-compatible output Negative strobe signal for channel D
SYNC 57 LVDS-compatible input Positive input for sync channel
SYNC 56 LVDS-compatible input Negative input for sync channel
TEMP 52 Analog output Die temperature
VCC 7, 16, 22, 31, 36, 38, 40, 43, 58, 60, 69, 77, 83, 86, 88, 93, 99 Power supply Positive supply, nominal 3.3 V