ZHCSA11H May   2012  – September 2024 TCA9548A

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 Reset Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET Input
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
      2. 7.5.2 Device Address
      3. 7.5.3 Bus Transactions
        1. 7.5.3.1 Writes
        2. 7.5.3.2 Reads
      4. 7.5.4 Control Register
      5. 7.5.5 RESET Input
      6. 7.5.6 Power-On Reset
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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Device Address

Figure 7-3 shows the address byte of the TCA9548A.

TCA9548A TCA9548A
                    Address Figure 7-3 TCA9548A Address

The last bit of the target address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation.

Table 7-1 shows the TCA9548A address reference.

Table 7-1 Address Reference
INPUTSI2C BUS TARGETADDRESS
A2A1A0
LLL112 (decimal), 70 (hexadecimal)
LLH113 (decimal), 71 (hexadecimal)
LHL114 (decimal), 72 (hexadecimal)
LHH115 (decimal), 73 (hexadecimal)
HLL116 (decimal), 74 (hexadecimal)
HLH117 (decimal), 75 (hexadecimal)
HHL118 (decimal), 76 (hexadecimal)
HHH119 (decimal), 77 (hexadecimal)