ZHCSA11G May   2012  – November 2019 TCA9548A

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用示意图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Input
      2. 8.4.2 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Device Address
      3. 8.5.3 Bus Transactions
        1. 8.5.3.1 Writes
        2. 8.5.3.2 Reads
      4. 8.5.4 Control Register
      5. 8.5.5 RESET Input
      6. 8.5.6 Power-On Reset
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
MIN MAX UNIT
STANDARD MODE
fscl I2C clock frequency 0 100 kHz
tsch I2C clock high time 4 μs
tscl I2C clock low time 4.7 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 250 ns
tsdh I2C serial-data hold time 0(1) μs
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 300 ns
tbuf I2C bus free time between stop and start 4.7 μs
tsts I2C start or repeated start condition setup 4.7 μs
tsth I2C start or repeated start condition hold 4 μs
tsps I2C stop condition setup 4 μs
tvdL(Data) Valid-data time (high to low)(3) SCL low to SDA output low valid 1 μs
tvdH(Data) Valid-data time (low to high)(3) SCL low to SDA output high valid 0.6 μs
tvd(ack) Valid-data time of ACK condition ACK signal from SCL low
to SDA output low
1 μs
Cb I2C bus capacitive load 400 pF
FAST MODE
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 μs
tscl I2C clock low time 1.3 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0(1) μs
ticr I2C input rise time 20 + 0.1Cb(2) 300 ns
ticf I2C input fall time 20 + 0.1Cb(2) 300 ns
tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 20 + 0.1Cb(2) 300 ns
tbuf I2C bus free time between stop and start 1.3 μs
tsts I2C start or repeated start condition setup 0.6 μs
tsth I2C start or repeated start condition hold 0.6 μs
tsps I2C stop condition setup 0.6 μs
tvdL(Data) Valid-data time (high to low)(3) SCL low to SDA output low valid 1 μs
tvdH(Data) Valid-data time (low to high)(3) SCL low to SDA output high valid 0.6 μs
tvd(ack) Valid-data time of ACK condition ACK signal from SCL low
to SDA output low
1 μs
Cb I2C bus capacitive load 400 pF
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge the undefined region of the falling edge of SCL.
Cb = total bus capacitance of one bus line in pF
Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 6)