SCPS222C May   2010  – October 2015 TCA8418E

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2C Interface Timing Requirements
    7. 6.7  Reset Timing Requirements for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I2C Bus
    8. 6.8  Switching Characteristics for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I2C Bus
    9. 6.9  Keypad Switching Characteristics for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I2C Bus
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Key Events
        1. 8.3.1.1 Key Event Table
        2. 8.3.1.2 General Purpose Input (GPI) Events
        3. 8.3.1.3 Key Event (FIFO) Reading
        4. 8.3.1.4 Key Event Overflow
      2. 8.3.2 Keypad Lock/Unlock
      3. 8.3.3 Keypad Lock Interrupt Mask Timer
      4. 8.3.4 Control-Alt-Delete Support
      5. 8.3.5 Interrupt Output
        1. 8.3.5.1 50-µs Interrupt Configuration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
      2. 8.4.2 Powered (Key Scan Mode)
        1. 8.4.2.1 Idle Key Scan Mode
        2. 8.4.2.2 Active Key Scan Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Bus Transactions
        1. 8.5.2.1 Writes
        2. 8.5.2.2 Reads
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
        1. 8.6.2.1  Configuration Register (Address 0x01)
        2. 8.6.2.2  Interrupt Status Register, INT_STAT (Address 0x02)
        3. 8.6.2.3  Key Lock and Event Counter Register, KEY_LCK_EC (Address 0x03)
        4. 8.6.2.4  Key Event Registers (FIFO), KEY_EVENT_A-J (Address 0x04-0x0D)
        5. 8.6.2.5  Keypad Lock1 to Lock2 Timer Register, KP_LCK_TIMER (Address 0x0E)
        6. 8.6.2.6  Unlock1 and Unlock2 Registers, UNLOCK1/2 (Address 0x0F-0x10)
        7. 8.6.2.7  GPIO Interrupt Status Registers, GPIO_INT_STAT1-3 (Address 0x11-0x13)
        8. 8.6.2.8  GPIO Data Status Registers, GPIO_DAT_STAT1-3 (Address 0x14-0x16)
        9. 8.6.2.9  GPIO Data Out Registers, GPIO_DAT_OUT1-3 (Address 0x17-0x19)
        10. 8.6.2.10 GPIO Interrupt Enable Registers, GPIO_INT_EN1-3 (Address 0x1A-0x1C)
        11. 8.6.2.11 Keypad or GPIO Selection Registers, KP_GPIO1-3 (Address 0x1D-0x1F)
        12. 8.6.2.12 GPI Event Mode Registers, GPI_EM1-3 (Address 0x20-0x22)
        13. 8.6.2.13 GPIO Data Direction Registers, GPIO_DIR1-3 (Address 0x23-0x25)
        14. 8.6.2.14 GPIO Edge/Level Detect Registers, GPIO_INT_LVL1-3 (Address 0x26-0x28)
        15. 8.6.2.15 Debounce Disable Registers, DEBOUNCE_DIS1-3 (Address 0x29-0x2B)
        16. 8.6.2.16 GPIO Pullup Disable Register, GPIO_PULL1-3 (Address 0x2C-0x2E)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Ghosting Considerations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing the Hardware Layout
        2. 9.2.2.2 Configuring the Registers
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8 Detailed Description

8.1 Overview

The TCA8418E supports up to 10 columns by 8 rows of keys, up to 80 keys. Any combination of these rows and columns can be configured to be added to the keypad matrix. This is done by setting the appropriate rows and columns to a value of 1 in the corresponding KP_GPIO registers (seen in Table 9). Once the rows and columns that are connected to the keypad matrix are added to the keypad array, then the TCA8418E will begin monitoring the keypad array, and any configured general purpose inputs (GPIs).

8.2 Functional Block Diagram

TCA8418E ld_cps181.gif Figure 20. Logic Diagram (Positive Logic)

8.3 Feature Description

8.3.1 Key Events

8.3.1.1 Key Event Table

The TCA8418E can be configured to support many different configurations of keypad setups. All 18 GPIOs for the rows and columns can be used to support up to 80 keys in a key pad array. Another option is that all 18 GPIOs be used for GPIs to read 18 buttons which are not connected in an array. Any combination in between is also acceptable (for example, a 3 x 4 keypad matrix and using the remaining 11 GPIOs as a combination of inputs and outputs).

For both types of inputs (keypad matrix and a GPI), a key event can be added to the key event FIFO. The values that are added to the FIFO depend on the configuration (keypad array or GPI) and on which port the press was read on. The tables below show the values that correspond to both types of configurations.

Key values below are represented in decimal values, because the 10s place is used to mark the row, and the ones place is used to denote the column. It is more clear to see the numbering convention used when viewed in decimal values.

Table 1. Key Event Table (Keypad Array)

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
R0 1 2 3 4 5 6 7 8 9 10
R1 11 12 13 14 15 16 17 18 19 20
R2 21 22 23 24 25 26 27 28 29 30
R3 31 32 33 34 35 36 37 38 39 40
R4 41 42 43 44 45 46 47 48 49 50
R5 51 52 53 54 55 56 57 58 59 60
R6 61 62 63 64 65 66 67 68 69 70
R7 71 72 73 74 75 76 77 78 79 80

Table 2. Key Event Table (Row GPI Events)

R0 R1 R2 R3 R4 R5 R6 R7
97 98 99 100 101 102 103 104

Table 3. Key Event Table (Column GPI Events)

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
105 106 107 108 109 110 111 112 113 114

8.3.1.2 General Purpose Input (GPI) Events

A column or row configured as GPI can be programmed to be part of the Key Event Table, hence becomes also capable of generating Key Event Interrupt. A Key Event Interrupt caused by a GPI follow the same process flow as a Key Event Interrupt caused by a Key press.

GPIs configured as part of the Key Event Table allows for single key switches to be monitored as well as other GPI interrupts. As part of the Event Table, GPIs are represented with decimal value of 97 and run through decimal value of 114. R0-R7 are represented by 97-104 and C0-C9 are represented by 105-114

For a GPI that is set as active high, and is enabled in the Key Event Table, the state-machine will add an event to the event count and event table whenever that GPI goes high. If the GPI is set to active low, a transition from high to low will be considered a press and will also be added to the event count and event table. Once the interrupt state has been met, the state machine will internally set an interrupt for the opposite state programmed in the register to avoid polling for the released state, hence saving current. Once the released state is achieved, it will add it to the event table. The press and release will still be indicated by bit 7 in the event register.

The GPI Events can also be used as unlocked sequences. When the GPI_EM bit is set, GPI events will not be tracked when the keypad is locked. GPI_EM bit must be cleared for the GPI events to be tracked in the event counter and table when the keypad is locked.

8.3.1.3 Key Event (FIFO) Reading

The TCA8418E has a 10-byte event FIFO, which stores any key presses or releases which have been configured to be added to the Key Event Table. All ROWs and COLs added to the keypad matrix via the KP_GPIO1-3 Registers will have any key pad events added to the FIFO. Any GPIs configured with a 1 in the GPI_EM1-3 Registers will also be part of the event FIFO.

When the host wishes to read the FIFO, the following procedure is recommended.

  1. Read the INT_STAT (0x02) register to determine what asserted the INT line. If GPI_INT or K_INT is set, then a key event has occurred, and the event is stored in the FIFO.
  2. Read the KEY_LCK_EC (0x03) register, bits [3:0] to see how many events are stored in FIFO.
  3. Read the KEY_EVENT_A (0x04) register. Bit 7 value '0' signifies key release, value 1 signifies key press. Bits [6:0] state which key was pressed with respect to the Key Event Table. With each read of the key event register, the event counter in KEY_LCK_EC[3:0] will decrease by 1, and the FIFO will shift the events down 1 register.
  4. Repeat step 3 until either KEY_LCK_EC[3:0] = 0 or KEY_EVENT_A = 0. This signifies that the FIFO is empty.
  5. Reset the INT_STAT interrupt flag which was causing the interrupt by writing a 1 to the specific bit.

As an example, consider the following key presses.

Table 4. Example Key Sequence

EVENT NUMBER KEY (DECIMAL VALUE) PRESS/RELEASE
1 1 Press
2 32 Press
3 1 Release
4 32 Release
5 23 Press
6 23 Release
7 45 Press
8 41 Press
9 41 Release
10 45 Release

If this example key sequence occurs, then while performing the recommended read procedure listed above, the host would see the following information. Information at the top of the list is of an initial read to the KEY_LCK_EC[3:0] register.

Table 5. Example Key Sequence

KEY_LCK_EC[3:0] VALUE KEY_EVENT_A VALUE (BINARY/HEX) KEY (DECIMAL VALUE) PRESS/RELEASE
10 N/A N/A N/A
9 1 000 0001 (0x81) 1 Press
8 1 010 0000 (0xA0) 32 Press
7 0 000 0001 (0x01) 1 Release
6 0 010 0000 (0x20) 32 Release
5 1 001 0111 (0x97) 23 Press
4 0 001 0111 (0x17) 23 Release
3 1 010 1101 (0xAD) 45 Press
2 1 010 1001 (0xA9) 41 Press
1 0 010 1001 (0x29) 41 Release
0 0 010 1101 (0x2D) 45 Release

8.3.1.4 Key Event Overflow

The TCA8418E has the ability to handle an overflow of the key event FIFO. An overflow event occurs when the FIFO is full of events (10 key events are stored) and a new key event occurs. In short, this means that the TCA8418E does not have the ability to hold any more key press information in the internal buffer. When this occurs, the OVR_FLOW_INT bit in the INT_STAT Register is set, and if the OVR_FLOW_IEN bit is set in the CFG Register, then the INT output will be asserted low to let the processor know that an overflow has occurred.

The TCA8418E has the ability to handle an overflow in 1 of two ways, which is determined by the bit value of the OVR_FLOW_M bit in the CFG Register.

Table 6. OVR_FLOW_M Bit

OVR_FLOW_M VALUE OVERFLOW MODE BEHAVIOR
1 Enabled Overflow data shifts with last event pushing first event out
0 Disabled (Default) Overflow data is not stored and lost

Consider the example below, if the FIFO is full of the key presses and a new key press comes in. This new overflow key press will be a key press of key 2 (0x82 is the hex representation of a key 2 press event)

Table 7. Key Event Overflow Handling

FIFO REGISTER ORIGINAL VALUE AFTER KEY 1 PRESS EVENT (0x82)
OVR_FLOW_M = 1 OVR_FLOW_M = 0
A 0x81 0xA0 0x81
B 0xA0 0x01 0xA0
C 0x01 0x20 0x01
D 0x20 0x97 0x20
E 0x97 0x17 0x97
F 0x17 0xAD 0x17
H 0xAD 0xA9 0xAD
I 0xA9 0x29 0xA9
J 0x29 0x2D 0x29
K 0x2D 0x82 0x2D

8.3.2 Keypad Lock/Unlock

This user can lock the keypad through the lock/unlock feature in this device. Once the keypad is locked by setting BIT6 in KEY_LCK_EC, it can prevent the generation of key event interrupts and recorded key events. The unlock keys can be programmed with any value of the keys in the keypad matrix or any general purpose input (GPI) values that are part of the Key Event Table. When the keypad lock interrupt mask timer is non-zero, the user will need to press two specific keys before an keylock interrupt is generated or keypad events are recorded. A key event interrupt is generated the first time a user presses any key. This first interrupt can be used to turn on an LCD and display the unlock message. The processor will then read the lock status register to see if the keypad is unlocked. The next interrupt (keylock interrupt) will not be generated unless both unlock keys sequences are correct. If correct Unlock keys are not pressed before the mask timer expires, the state machine will start over again.

The recommended procedure to lock the keypad is to do the following

  1. Determine which keys will be used for the unlock sequence. The key value from the Key Event Tables needs to be entered into the UNLOCK1 and UNLOCK2 registers.
  2. The UNLOCK1 to UNLOCK2 timer duration must be set by entering the desired seconds (valid range is 0 to 7 seconds) into bits [2:0] of the KP_LCK_TMR register.
  3. If an interrupt mask is desired (see Keypad Lock Interrupt Mask Timer), then the desired interrupt mask duration (valid range is 0 to 31 seconds) must be entered into bits [7:3] of the KP_LCK_TMR register.
  4. When the host is ready to lock the keypad, a 1 is to be written to the K_LCK_EN bit (BIT6) in the KEY_LCK_EC register. This will lock the keypad.
  5. If the host wishes to manually unlock the keypad, writing a '0' to the K_LCK_EN bit (BIT6) in the KEY_LCK_EC register will unlock the keypad.
TCA8418E KeylockFlowchart.gif Figure 21. Keypad Lock Flowchart

8.3.3 Keypad Lock Interrupt Mask Timer

The TCA8418E features a Keypad Lock/Unlock feature which allows the user to stop the generation of key event interrupts by locking the key pad. There is an interrupt mask timer feature with the keypad lock, which allows the generation of a single interrupt when a key is pressed, primarily for the purpose of LCD backlighting. Note that this interrupt mask timer can also be used to limit the number of interrupts generated for a given amount of time.

The interrupt mask timer is enabled by setting bits [7:3] of the KP_LCK_TIMER register. The value in this register can be anywhere from 0 to 31 seconds (note that a value of 0 will disable this interrupt mask feature). When a keypad is locked and the interrupt mask timer is set to a non-zero value, this will enable the interrupt mask timer. This interrupt mask timer limits the amount of interrupts generated. Typically, this is used with the Keypad Lock/Unlock feature for LCD back lights. It is easiest to explain this feature with the following example; A mobile device has a LCD screen with a back light display which turns off after 10 seconds to save power. Normally, an interrupt to the processor would tell this LCD back light to turn on. When the keypad is locked, no interrupts are generated, so the back light will never turn on. This is where the interrupt mask feature is used. Please refer to Figure 21. The procedure for an example is below.

  1. Since the back light turns off after 10 seconds of no interrupts, the interrupt mask timer ( KP_LCK_TIMER[7:3] ) gets set to 10 seconds. Keypad is then locked.
  2. When the first key press is detected, the TCA8418E sends an interrupt to the processor and starts a 10 second count down.
  3. If the correct unlock sequence is not entered within the 10 seconds, no interrupts are sent and the back light will turn off.
  4. After the 10 second timer has expired, if another key press occurs while keypad is locked (regardless of whether it is a correct unlock key or not), another interrupt is generated and the 10 second count down begins again.

8.3.4 Control-Alt-Delete Support

The TCA8418E can support normal key presses, but it also can support a <Ctrl><Alt><Del> (CAD) key press. This feature allows the host to recognize a specific key press and alert the host that the combination has occurred. The TCA8418E will recognize a <Ctrl><Alt><Del> key press if keys 1, 11, and 21 are all pressed at the same time. These keys are referenced to the key values listed in the Key Event Table. Note that this key combination that triggers a CAD interrupt is not adjustable, and must be keys 1, 11, and 21. On the YFP package, there is an additional CAD_INT output, which will be asserted low when the <1><11><21> keys are pressed at the same time.

8.3.5 Interrupt Output

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the input port register.

The INT output has an open-drain structure and requires a pullup resistor to VCC depending on the application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA8418E, then the INT pin has to be connected to VCC. If not, the INT pin can be connected to VCCP.

8.3.5.1 50-µs Interrupt Configuration

The TCA8418E provides the capability of deasserting the interrupt for 50 μs while there is a pending event. When the INT_CFG bit in Register 0x01 is set, any attempt to clear the interrupt bit while the interrupt pin is already asserted results in a 50 μs deassertion. When the INT_CFG bit is cleared, INT remains asserted if the host tries to clear the interrupt. This feature is particularly useful for software development and edge triggering applications.

8.4 Device Functional Modes

8.4.1 Power-On Reset (POR)

When power (from 0 V) is applied to VCC, an internal power-on reset circuit holds the TCA8418E in a reset condition until VCC has reached VPORR. At that time, the reset condition is released, and the TCA8418E registers and I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below VPORF and back up to the operating voltage for a power-reset cycle. See Power Supply Recommendations for more information on power up reset requirements.

8.4.2 Powered (Key Scan Mode)

The TCA8418E can be used to read GPI from single buttons, or configured in key scan mode to read an array of keys. In key scan mode, there are two modes of operation.

8.4.2.1 Idle Key Scan Mode

Once the TCA8418E has had the keypad array configured, it will enter idle mode when no keys are being pressed. All columns configured as part of the keypad array will be driven low and all rows configured as part of the keypad array will be set to inputs, with pullup resistors enabled. During idle mode, the internal oscillator is turned off so that power consumption is low as the device awaits a key press.

8.4.2.2 Active Key Scan Mode

When the TCA8418E is in idle key scan mode, the device awaits a key press. Once a key is pressed in the array, a low signal on one of the ROW pin inputs triggers an interrupt, which will turn on the internal oscillator and enter the active key scan mode. At this point, the TCA8418E will start the key scan algorithm to determine which key is being pressed, and/or it will use the internal oscillator for debouncing. Once all keys have been released, the device will enter idle key scan mode.

8.5 Programming

8.5.1 I2C Interface

The TCA8418E has a standard bidirectional I2C interface that is controlled by a master device in order to be configured or read the status of this device. Each slave on the I2C bus has a specific device address to differentiate between other slave devices that are on the same I2C bus. Many slave devices will require configuration upon startup to set the behavior of the device. This is typically done when the master accesses internal register maps of the slave, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read.

The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pullup resistor. The size of the pullup resistor is determined by the amount of capacitance on the I2C lines. (For further details, refer to I2C pullup Resistor Calculation (SLVA689).) Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition.

The following is the general procedure for a master to access a slave device:

  1. If a master wants to send data to a slave:
    • Master-transmitter sends a START condition and addresses the slave-receiver.
    • Master-transmitter sends data to slave-receiver.
    • Master-transmitter terminates the transfer with a STOP condition.
  2. If a master wants to receive or read data from a slave:
    • Master-receiver sends a START condition and addresses the slave-transmitter.
    • Master-receiver sends the requested register to read to slave-transmitter.
    • Master-receiver receives data from the slave-transmitter.
    • Master-receiver terminates the transfer with a STOP condition.
TCA8418E I2C_START_STOP.gif Figure 22. Definition of Start and Stop Conditions
TCA8418E I2C_Data_Byte.gif Figure 23. Bit Transfer

8.5.2 Bus Transactions

Data must be sent to and received from the slave devices, and this is accomplished by reading from or writing to registers in the slave device.

Registers are locations in the memory of the slave which contain information, whether it be the configuration information or some sampled data to send back to the master. The master must write information to these registers in order to instruct the slave device to perform a task.

While it is common to have registers in I2C slaves, note that not all slave devices will have registers. Some devices are simple and contain only 1 register, which may be written to directly by sending the register data immediately after the slave address, instead of addressing a register. An example of a single-register device would be an 8-bit I2C switch, which is controlled via I2C commands. Since it has 1 bit to enable or disable a channel, there is only 1 register needed, and the master merely writes the register data after the slave address, skipping the register number.

8.5.2.1 Writes

To write on the I2C bus, the master will send a START condition on the bus with the address of the slave, as well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master will then send the register address of the register to which it wishes to write. The slave will acknowledge again, letting the master know it is ready. After this, the master will start sending the register data to the slave until the master has sent all the data necessary (which is sometimes only a single byte), and the master will terminate the transmission with a STOP condition.

Figure 24 shows an example of writing a single byte to a register.

TCA8418E i2c_write.gif Figure 24. Write to Register
TCA8418E i2c_example.gif Figure 25. Write to Configuration Register

8.5.2.2 Reads

Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave, the master must first instruct the slave which register it wishes to read from. This is done by the master starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. Once the slave acknowledges this register address, the master will send a START condition again, followed by the slave address with the R/W bit set to 1 (signifying a read). This time, the slave will acknowledge the read request, and the master will release the SDA bus but will continue supplying the clock to the slave. During this part of the transaction, the master will become the master-receiver, and the slave will become the slave-transmitter.

The master will continue to send out the clock pulses, but will release the SDA line so that the slave can transmit data. At the end of every byte of data, the master will send an ACK to the slave, letting the slave know that it is ready for more data. Once the master has received the number of bytes it is expecting, it will send a NACK, signaling to the slave to halt communications and release the bus. The master will follow this up with a STOP condition.

Figure 26 shows an example of reading a single byte from a slave register.

TCA8418E i2c_read_example.gif Figure 26. Read from Register

8.6 Register Maps

8.6.1 Device Address

The address of the TCA8418E is shown in Table 8.

Table 8. TCA8418E Device Addresses

BYTE BIT
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C slave address 0 1 1 0 1 0 0 R/W

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is stored in the control register in the TCA8418E. The command byte indicates the register that will be updated with information. All registers can be read and written to by the system master.

Table 9 shows all the registers within this device and their descriptions. The default value in all registers is 0.

Table 9. Register Descriptions

ADDRESS REGISTER NAME REGISTER
DESCRIPTION
7 6 5 4 3 2 1 0
0x00 Reserved Reserved
0x01 CFG Configuration register
(interrupt processor interrupt enables)
AI GPI_E_CGF OVR_FLOW_M INT_ CFG OVR_FLOW_IEN K_LCK_IEN GPI_IEN KE_IEN
0x02 INT_STAT Interrupt status register N/A
0
N/A
0
N/A
0
CAD_INT OVR_FLOW_INT K_LCK_INT GPI_ INT K_ INT
0x03 KEY_LCK_EC Key lock and event counter register N/A
0
K_LCK_EN LCK2 LCK1 KLEC3 KLEC2 KLEC1 KLEC0
0x04 KEY_EVENT_A Key event register A KEA7
0
KEA6
0
KEA5
0
KEA4
0
KEA3
0
KEA2
0
KEA1
0
KEA0
0
0x05 KEY_EVENT_B Key event register B KEB7
0
KEB6
0
KEB5
0
KEB4
0
KEB3
0
KEB2
0
KEB1
0
KEB0
0
0x06 KEY_EVENT_C Key event register C KEC7
0
KEC6
0
KEC5
0
KEC4
0
KEC3
0
KEC2
0
KEC1
0
KEC0
0
0x07 KEY_EVENT_D Key event register D KED7
0
KED6
0
KED5
0
KED4
0
KED3
0
KED2
0
KED1
0
KED0
0
0x08 KEY_EVENT_E Key event register E KEE7
0
KEE6
0
KEE5
0
KEE4
0
KEE3
0
KEE2
0
KEE1
0
KEE0
0
0x09 KEY_EVENT_F Key event register F KEF7
0
KEF6
0
KEF5
0
KEF4
0
KEF3
0
KEF2
0
KEF1
0
KEF0
0
0x0A KEY_EVENT_G Key event register G KEG7
0
KEG6
0
KEG5
0
KEG4
0
KEG3
0
KEG2
0
KEG1
0
KEG0
0
0x0B KEY_EVENT_H Key event register H KEH7
0
KEH6
0
KEH5
0
KEH4
0
KEH3
0
KEH2
0
KEH1
0
KEH0
0
0x0C KEY_EVENT_I Key event register I KEI7
0
KEI6
0
KEI5
0
KEI4
0
KEI3
0
KEI2
0
KEI1
0
KEI0
0
0x0D KEY_EVENT_J Key event register J KEJ7
0
KEJ6
0
KEJ5
0
KEJ64
0
KEJ3
0
KEJ2
0
KEJ1
0
KEJ0
0
0x0E KP_LCK_TIMER Keypad lock 1 to lock 2 timer KL7 KL6 KL5 KL4 KL3 KL2 KL1 KL0
0x0F UNLOCK1 Unlock key 1 UK1_7 UK1_6 UK1_5 UK1_4 UK1_3 UK1_2 UK1_1 UK1_0
0x10 UNLOCK1 Unlock key2 UK2_7 UK2_6 UK2_5 UK2_4 UK2_3 UK2_2 UK2_1 UK2_0
0x11 GPIO_INT_STAT1 GPIO interrupt status R7IS
0
R6IS
0
R5IS
0
R4IS
0
R3IS
0
R2IS
0
R1IS
0
R0IS
0
0x12 GPIO_INT_STAT2 GPIO interrupt status C7IS
0
C6IS
0
C5IS
0
C4IS
0
C3IS
0
C2IS
0
C1IS
0
C0IS
0
0x13 GPIO_INT_STAT3 GPIO interrupt status N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
C9IS
0
C8IS
0
0x14 GPIO_DAT_STAT1 (read twice to clear) GPIO data status R7DS R6DS R5DS R4DS R3DS R2DS R1DS R0DS
0x15 GPIO_DAT_STAT2 (read twice to clear) GPIO data status C7DS C6DS C5DS C4DS C3DS C2DS C1DS C0DS
0x16 GPIO_DAT_STAT3 (read twice to clear) GPIO data status N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
C9DS C8DS
0x17 GPIO_DAT_OUT1 GPIO data out R7DO
0
R6DO
0
R5DO
0
R4DO
0
R3DO
0
R2DO
0
R1DO
0
R0DO
0
0x18 GPIO_DAT_OUT2 GPIO data out C7DO
0
C6DO
0
C5DO
0
C4DO
0
C3DO
0
C2DO
0
C1DO
0
C0DO
0
0x19 GPIO_DAT_OUT3 GPIO data out N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
C9DO
0
C8DO
0
0x1A GPIO_INT_EN1 GPIO interrupt enable R7IE
0
R6IE
0
R5IE
0
R4IE
0
R3IE
0
R2IE
0
R1IE
0
R0IE
0
0x1B GPIO_INT_EN2 GPIO interrupt enable C7IE
0
C6IE
0
C5IE
0
C4IE
0
C3IE
0
C2IE
0
C1IE
0
C0IE
0
0x1C GPIO_INT_EN3 GPIO interrupt enable N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
C9IE
0
C8IE
0
0x1D KP_GPIO1 Keypad or GPIO selection

0: GPIO

1: KP matrix

ROW7
0
ROW6
0
ROW5
0
ROW4
0
ROW3
0
ROW2
0
ROW1
0
ROW0
0
0x1E KP_GPIO2 Keypad or GPIO selection

0: GPIO

1: KP matrix

COL7
0
COL6
0
COL5
0
COL4
0
COL3
0
COL2
0
COL1
0
COL0
0
0x1F KP_GPIO3 Keypad or GPIO selection

0: GPIO

1: KP matrix

N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
COL9
0
COL8
0
0x20 GPI_EM1 GPI event mode 1 ROW7
0
ROW6
0
ROW5
0
ROW4
0
ROW3
0
ROW2
0
ROW1
0
ROW0
0
0x21 GPI_EM2 GPI event mode 2 COL7
0
COL6
0
COL5
0
COL4
0
COL3
0
COL2
0
COL1
0
COL0
0
0x22 GPI_EM3 GPI event mode 3 N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
COL9
0
COL8
0
0x23 GPIO_DIR1 GPIO data direction

0: input

1: output

R7DD
0
R6DD
0
R5DD
0
R4DD
0
R3DD
0
R2DD
0
R1DD
0
R0DD
0
0x24 GPIO_DIR2 GPIO data direction

0: input

1: output

C7DD
0
C6DD
0
C5DD
0
C4DD
0
C3DD
0
C2DD
0
C1DD
0
C0DD
0
0x25 GPIO_DIR3 GPIO data direction

0: input

1: output

N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
C9DD
0
C8DD
0
0x26 GPIO_INT_LVL1 GPIO edge/level detect

0: falling/low

1: rising/high

R7IL
0
R6IL
0
R5IL
0
R4IL
0
R3IL
0
R2IL
0
R1IL
0
R0IL
0
0x27 GPIO_INT_LVL2 GPIO edge/level detect

0: falling/low

1: rising/high

C7IL
0
C6IL
0
C5IL
0
C4IL
0
C3IL
0
C2IL
0
C1IL
0
C0IL
0
0x28 GPIO_INT_LVL3 GPIO edge/level detect

0: falling/low

1: rising/high

N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
C9IL
0
C8IL
0
0x29 DEBOUNCE_DIS1 Debounce disable

0: debounce enabled

1: debounce disabled

R7DD
0
R6DD
0
R5DD
0
R4DD
0
R3DD
0
R2DD
0
R1DD
0
R0DD
0
0x2A DEBOUNCE_DIS2 Debounce disable

0: debounce enabled

1: debounce disabled

C7DD
0
C6DD
0
C5DD
0
C4DD
0
C3DD
0
C2DD
0
C1DD
0
C0DD
0
0x2B DEBOUNCE_DIS3 Debounce disable

0: debounce enabled

1: debounce disabled

N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
C9DD
0
C8DD
0
0x2C GPIO_PULL1 GPIO pullup disable

0: pullup enabled

1: pullup disabled

R7PD
0
R6PD
0
R5PD
0
R4PD
0
R3PD
0
R2PD
0
R1PD
0
R0PD
0
0x2D GPIO_PULL2 GPIO pullup disable

0: pullup enabled

1: pullup disabled

C7PD
0
C6PD
0
C5PD
0
C4PD
0
C3PD
0
C2PD
0
C1PD
0
C0PD
0
0x2E GPIO_PULL3 GPIO pullup disable

0: pullup enabled

1: pullup disabled

N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
N/A
0
C9PD
0
C8PD
0
0x2F Reserved

8.6.2.1 Configuration Register (Address 0x01)

Table 10. Configuration Register Field Descriptions

BIT NAME DESCRIPTION
7 AI

Auto-increment for read and write operations; See below table for more information

0 = disabled

1 = enabled

6 GPI_E_CFG

GPI event mode configuration

0 = GPI events are tracked when keypad is locked

1 = GPI events are not tracked when keypad is locked

5 OVR_FLOW_M

Overflow mode

0 = disabled; Overflow data is lost

1 = enabled; Overflow data shifts with last event pushing first event out

4 INT_CFG

Interrupt configuration

0 = processor interrupt remains asserted (or low) if host tries to clear interrupt while there is still a pending key press, key release or GPI interrupt

1 = processor interrupt is deasserted for 50 μs and reassert with pending interrupts

3 OVR_FLOW_IEN

Overflow interrupt enable

0 = disabled; INT is not asserted if the FIFO overflows

1 = enabled; INT becomes asserted if the FIFO overflows

2 K_LCK_IEN

Keypad lock interrupt enable

0 = disabled; INT is not asserted after a correct unlock key sequence

1 = enabled; INT becomes asserted after a correct unlock key sequence

1 GPI_IEN

GPI interrupt enable to host processor

0 = disabled; INT is not asserted for a change on a GPI

1 = enabled; INT becomes asserted for a change on a GPI

0 KE_IEN

Key events interrupt enable to host processor

0 = disabled; INT is not asserted when a key event occurs

1 = enabled; INT becomes asserted when a key event occurs

Bit 7 in this register is used to determine the programming mode. If it is low, all data bytes are written to the register defined by the command byte. If bit 7 is high, the value of the command byte is automatically incremented after each byte is written, and the next data byte is stored in the corresponding register. Registers are written in the sequence shown in Table 9. Once the GPIO_PULL3 register (0x2E) is written to, the command byte returns to register 0. Registers 0 and 2F are reserved and a command byte that references these registers is not acknowledged by the TCA8418E.

The keypad lock interrupt enable determines if the interrupt pin is asserted when the key lock interrupt (see Interrupt Status Register) bit is set.

8.6.2.2 Interrupt Status Register, INT_STAT (Address 0x02)

Table 11. Interrupt Status Register Field Descriptions

BIT NAME DESCRIPTION
7 N/A Always 0
6 N/A Always 0
5 N/A Always 0
4 CAD_INT

CTRL-ALT-DEL key sequence status. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

1 = interrupt detected

3 OVR_FLOW_INT

Overflow interrupt status. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

1 = interrupt detected

2 K_LCK_INT

Keypad lock interrupt status. This is the interrupt to the processor when the keypad lock sequence is started. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

1 = interrupt detected

1 GPI_INT

GPI interrupt status. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

1 = interrupt detected

Can be used to mask interrupts

0 K_INT

Key events interrupt status. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

1 = interrupt detected

The INT_STAT register is used to check which type of interrupt has been triggered. If the corresponding interrupt enable bits are set in the Configuration Register, then a value of 1 in the corresponding bit will assert the INT line low. An exception to this is the CAD_INT bit, which will assert the CAD_INT pin on YFP packages.

A read to this register will return which types of events have occurred. Writing a 1 to the bit will clear the interrupt, unless there is still data which has set the Interrupt (unread keys in the FIFO).

8.6.2.3 Key Lock and Event Counter Register, KEY_LCK_EC (Address 0x03)

Table 12. Key Lock and Event Counter Register Field Descriptions

BIT NAME DESCRIPTION
7 N/A Always 0
6 K_LCK_EN

Key lock enable

0 = disabled; Write a 0 to this bit to unlock the keypad manually

1 = enabled; Write a 1 to this bit to lock the keypad

5 LCK2

Keypad lock status

0 = unlock (if LCK1 is 0 too)

1 = locked (if LCK1 is 1 too)

4 LCK1

Keypad lock status

0 = unlock (if LCK2 is 0 too)

1 = locked (if LCK2 is 1 too)

3 KEC3 Key event count, Bit 3
2 KEC2 Key event count, Bit 2
1 KEC1 Key event count, Bit 1
0 KEC0 Key event count, Bit 0

KEC[3:0] indicates how many key events are in the FIFO. For example, KEC[3:0] = 0b0000 = 0 events, KEC[3:0] = 0b0001 = 1 event and KEC[3:0] = 0b1010 = 10 events. As events happen (press or release), the count increases accordingly.

8.6.2.4 Key Event Registers (FIFO), KEY_EVENT_A–J (Address 0x04–0x0D)

Table 13. Key Event Register Field Descriptions

ADDRESS REGISTER NAME(1) REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x04 KEY_EVENT_A Key event register A KEA7 KEA6 KEA5 KEA4 KEA3 KEA2 KEA1 KEA0
(1) Only KEY_EVENT_A register is shown

These registers – KEY_EVENT_A-J – function as a FIFO stack which can store up to 10 key presses and releases. The user first checks the INT_STAT register to see if there are any interrupts. If so, then the Key Lock and Event Counter Register (KEY_LCK_EC, register 0x03) is read to see how many interrupts are stored. The INT_STAT register is then read again to ensure no new events have come in. The KEY_EVENT_A register is then read as many times as there are interrupts. Each time a read happens, the count in the KEY_LCK_EC register reduces by 1. The data in the FIFO also moves down the stack by 1 too (from KEY_EVENT_J to KEY_EVENT_A). Once all events have been read, the key event count is at 0 and then KE_INT bit can be cleared by writing a ‘1’ to it.

In the KEY_EVENT_A register, KEA[6:0] indicates the key # pressed or released. A value of 0 to 80 indicate which key has been pressed or released in a keypad matrix. Values of 97 to 114 are for GPI events.

Bit 7 or KEA[7] indicate if a key press or key release has happened. A ‘0’ means a key release happened. A ‘1’ means a key has been pressed (which can be cleared on a read).

For example, 3 key presses and 3 key releases are stored as 6 words in the FIFO. As each word is read, the user knows if it is a key press or key release that occurred. Key presses such as CTRL+ALT+DEL are stored as 3 simultaneous key presses. Key presses and releases generate key event interrupts. The KE_INT bit and /INT pin will not cleared until the FIFO is cleared of all events.

All registers can be read but for the purpose of the FIFO, the user should only read KEY_EVENT_A register. Once all the events in the FIFO have been read, reading of KEY_EVENT_A register will yield a zero value.

8.6.2.5 Keypad Lock1 to Lock2 Timer Register, KP_LCK_TIMER (Address 0x0E)

Table 14. Keypad Lock1 to Lock2 Timer Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x0E KP_LCK_TIMER Keypad lock interrupt mask timer and lock 1 to lock 2 timer KL7 KL6 KL5 KL4 KL3 KL2 KL1 KL0

KL[2:0] are for the Lock1 to Lock2 timer

KL[7:3] are for the interrupt mask timer

Lock1 to Lock2 timer must be non-zero for keylock to be enabled. The lock1 to lock2 bits ( KL[2:0] ) define the time in seconds the user has to press unlock key 2 after unlock key 1 before the key lock sequence times out. For more information, please see Keypad Lock/Unlock.

If the keypad lock interrupt mask timer is non-zero, a key event interrupt (K_INT) will be generated on any first key press. The second interrupt (K_LCK_IN) will only be generated when the correct unlock sequence has been completed. If either timer expires, the keylock state machine will reset.

When the interrupt mask timer is disabled (‘0’), a key lock interrupt will trigger only when the correct unlock sequence is completed.

The interrupt mask timer should be set for the time it takes for the LCD to dim or turn off. For more information, please see Keypad Lock Interrupt Mask Timer.

8.6.2.6 Unlock1 and Unlock2 Registers, UNLOCK1/2 (Address 0x0F-0x10)

Table 15. Unlock1 and Unlock2 Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x0F Unlock1 Unlock key 1 UK1_7 UK1_6 UK1_5 UK1_4 UK1_3 UK1_2 UK1_1 UK1_0
0x10 Unlock2 Unlock key 2 UK2_7 UK2_6 UK2_5 UK2_4 UK2_3 UK2_2 UK2_1 UK2_0

UK1[6:0] contains the key number used to unlock key 1

UK2[6:0] contains the key number used to unlock key 2

A ‘0’ in either register will disable the keylock function.

8.6.2.7 GPIO Interrupt Status Registers, GPIO_INT_STAT1–3 (Address 0x11–0x13)

These registers are used to check GPIO interrupt status. If the GPI_INT bit is set in INT_STAT register, then the GPI which set that interrupt will be marked with a 1 in the corresponding table. To clear the GPI_INT bit, these registers must all be 0x00. A read to the register will clear it.

Table 16. GPIO Interrupt Status Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x11 GPIO_INT_STAT1 GPIO Interrupt Status 1 R7IS R6IS R5IS R4IS R3IS R2IS R1IS R0IS
0x12 GPIO_INT_STAT2 GPIO Interrupt Status 2 C7IS C6IS C5IS C4IS C3IS C2IS C1IS C0IS
0x13 GPIO_INT_STAT3 GPIO Interrupt Status 3 N/A N/A N/A N/A N/A N/A C9IS C8IS

8.6.2.8 GPIO Data Status Registers, GPIO_DAT_STAT1–3 (Address 0x14–0x16)

These registers show the GPIO state when read for inputs and outputs. Read these twice to clear them.

Table 17. GPIO Data Status Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x14 GPIO_DAT_STAT1 GPIO Data Status 1 R7DS R6DS R5DS R4DS R3DS R2DS R1DS R0DS
0x15 GPIO_DAT_STAT2 GPIO Data Status 2 C7DS C6DS C5DS C4DS C3DS C2DS C1DS C0DS
0x16 GPIO_DAT_STAT3 GPIO Data Status 3 N/A N/A N/A N/A N/A N/A C9DS C8DS

8.6.2.9 GPIO Data Out Registers, GPIO_DAT_OUT1–3 (Address 0x17–0x19)

These registers contain GPIO data to be written to GPIO out driver; inputs are not affected. This sets the output for the corresponding GPIO output.

Table 18. GPIO Data Out Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x17 GPIO_DAT_OUT1 GPIO Data Out 1 R7DO R6DO R5DO R4DO R3DO R2DO R1DO R0DO
0x18 GPIO_DAT_OUT2 GPIO Data Out 2 C7DO C6DO C5DO C4DO C3DO C2DO C1DO C0DO
0x19 GPIO_DAT_OUT3 GPIO Data Out 3 N/A N/A N/A N/A N/A N/A C9DO C8DO

8.6.2.10 GPIO Interrupt Enable Registers, GPIO_INT_EN1–3 (Address 0x1A–0x1C)

These registers enable interrupts (bit value 1) or disable interrupts (bit value '0') for general purpose inputs (GPI) only. If the input changes on a pin which is setup as a GPI, then the GPI_INT bit will be set in the INT_STAT register.

A bit value of '0' in any of the unreserved bits disables the corresponding pin's ability to generate an interrupt when the state of the input changes. This is the default value.

A bit value of 1 in any of the unreserved bits enables the corresponding pin's ability to generate an interrupt when the state of the input changes.

Table 19. GPIO Interrupt Enable Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x1A GPIO_INT_EN1 GPIO Interrupt Enable 1 R7IE R6IE R5IE R4IE R3IE R2IE R1IE R0IE
0x1B GPIO_INT_EN2 GPIO Interrupt Enable 2 C7IE C6IE C5IE C4IE C3IE C2IE C1IE C0IE
0x1C GPIO_INT_EN3 GPIO Interrupt Enable 3 N/A N/A N/A N/A N/A N/A C9IE C8IE

8.6.2.11 Keypad or GPIO Selection Registers, KP_GPIO1–3 (Address 0x1D–0x1F)

A bit value of '0' in any of the unreserved bits puts the corresponding pin in GPIO mode. A pin in GPIO mode can be configured as an input or an output in the GPIO_DIR1-3 registers. This is the default value.

A 1 in any of these bits puts the pin in key scan mode and becomes part of the keypad array, then it is configured as a row or column accordingly (this is not adjustable).

Table 20. Keypad or GPIO Selection Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x1D KP_GPIO1 Keypad/GPIO Select 1 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0
0x1E KP_GPIO2 Keypad/GPIO Select 2 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0
0x1F KP_GPIO3 Keypad/GPIO Select 3 N/A N/A N/A N/A N/A N/A COL9 COL8

8.6.2.12 GPI Event Mode Registers, GPI_EM1–3 (Address 0x20–0x22)

A bit value of '0' in any of the unreserved bits indicates that it is not part of the event FIFO. This is the default value.

A 1 in any of these bits means it is part of the event FIFO. When a pin is setup as a GPI and has a value of 1 in the Event Mode register, then any key presses will be added to the FIFO. Please see Key Event Table for more information.

Table 21. GPI Event Mode Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x20 GPI_EM1 GPI Event Mode Select 1 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0
0x21 GPI_EM2 GPI Event Mode Select 2 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0
0x23 GPI_EM3 GPI Event Mode Select 3 N/A N/A N/A N/A N/A N/A COL9 COL8

8.6.2.13 GPIO Data Direction Registers, GPIO_DIR1–3 (Address 0x23–0x25)

A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. This is the default value.

A 1 in any of these bits sets the pin as an output.

Table 22. GPIO Data Direction Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x23 GPIO_DIR1 GPIO Direction 1 R7DD R6DD R5DD R4DD R3DD R2DD R1DD R0DD
0x24 GPIO_DIR2 GPIO Direction 2 C7DD C6DD C5DD C4DD C3DD C2DD C1DD C0DD
0x25 GPIO_DIR3 GPIO Direction 3 N/A N/A N/A N/A N/A N/A C9DD C8DD

8.6.2.14 GPIO Edge/Level Detect Registers, GPIO_INT_LVL1–3 (Address 0x26–0x28)

A bit value of '0' indicates that interrupt will be triggered on a high-to-low/low-level transition for the inputs in GPIO mode. This is the default value.

A bit value of 1 indicates that interrupt will be triggered on a low-to-high/high-level value for the inputs in GPIO mode.

Table 23. GPIO Edge/Level Detect Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x26 GPIO_INT_LVL1 GPIO Edge/Level Detect 1 R7IL R6IL R5IL R4IL R3IL R2IL R1IL R0IL
0x27 GPIO_INT_LVL2 GPIO Edge/Level Detect 2 C7IL C6IL C5IL C4IL C3IL C2IL C1IL C0IL
0x28 GPIO_INT_LVL3 GPIO Edge/Level Detect 3 N/A N/A N/A N/A N/A N/A C9IL C8IL

8.6.2.15 Debounce Disable Registers, DEBOUNCE_DIS1–3 (Address 0x29–0x2B)

This is for pins configured as inputs. A bit value of ‘0’ in any of the unreserved bits enables the debounce. This is the default value

A bit value of ‘1’ disables the debounce.

Table 24. Debounce Disable Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x29 DEBOUNCE_DIS1 Debounce Disable 1 R7DD R6DD R5DD R4DD R3DD R2DD R1DD R0DD
0x30 DEBOUNCE_DIS2 Debounce Disable 2 C7DD C6DD C5DD C4DD C3DD C2DD C1DD C0DD
0x2B DEBOUNCE_DIS3 Debounce Disable 3 N/A N/A N/A N/A N/A N/A C9DD C8DD
TCA8418E debounce_scps222.gif Figure 27. Debounce Enabled and Disabled

Debounce disable will have the same effect for GPI mode or for rows in keypad scanning mode. The RESET input always has a 50-μs debounce time.

The debounce time for inputs is the time required for the input to be stable to be noticed. This time is 50 μs.

The debounce time for the keypad is for the columns only. The minimum time is 25 ms. All columns are scanned once every 25 ms to detect any key presses. Two full scans are required to see if any keys were pressed. If the first scan is done just after a key press, it will take 25 ms to detect the key press. If the first scan is down much later than the key press, it will take 40 ms to detect a key press.

8.6.2.16 GPIO Pullup Disable Register, GPIO_PULL1–3 (Address 0x2C–0x2E)

This register enables or disables pullup registers from inputs.

A bit value of '0' will enable the internal pullup resistors. This is the default value.

A bit value of 1 will disable the internal pullup resistors.

Table 25. GPIO Pullup Disable Register Field Descriptions

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT
7 6 5 4 3 2 1 0
0x2C GPIO_PULL1 GPIO pullup Disable 1 R7PD R6PD R5PD R4PD R3PD R2PD R1PD R0PD
0x3D GPIO_PULL2 GPIO pullup Disable 2 C7PD C6PD C5PD C4PD C3PD C2PD C1PD C0PD
0x2E GPIO_PULL3 GPIO pullup Disable 3 N/A N/A N/A N/A N/A N/A C9PD C8PD