ZHCSJT7
May 2019
TAS5806MD
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
4
修订历史记录
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
7.7.1
Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode
7.7.2
Bridge Tied Load (BTL) Configuration Curves
7.7.3
Parallel Bridge Tied Load (PBTL) Configuration
7.7.4
Headphone Driver
7.7.5
Line Driver
8
Parametric Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Power Supplies
9.3.2
Device Clocking
9.3.3
Serial Audio Port – Clock Rates
9.3.4
Clock Halt Auto-recovery
9.3.5
Sample Rate on the Fly Change
9.3.6
Serial Audio Port - Data Formats and Bit Depths
9.3.7
Digital Audio Processing
9.3.8
Class D Audio Amplifier
9.3.8.1
Speaker Amplifier Gain Select
9.4
Device Functional Modes
9.4.1
Software Control
9.4.2
Speaker Amplifier Operating Modes
9.4.2.1
BTL Mode
9.4.2.2
PBTL Mode
9.4.3
Low EMI Modes
9.4.3.1
Minimize EMI with Spread Spectrum
9.4.3.2
Channel to Channel Phase shift
9.4.3.3
Multi-Devices PWM Phase Synchronization
9.4.4
Thermal Foldback
9.4.5
Headphone Control
9.4.6
Device State Control
9.4.7
Device Modulation
9.4.7.1
BD Modulation
9.4.7.2
1SPW Modulation
9.4.7.3
Hybrid Modulation
9.5
Programming and Control
9.5.1
I2 C Serial Communication Bus
9.5.2
Slave Address
9.5.2.1
Random Write
9.5.2.2
Sequential Write
9.5.2.3
Random Read
9.5.2.4
Sequential Read
9.5.2.5
DSP Memory Book, Page and BQ update
9.5.2.6
Example Use
9.5.2.7
Checksum
9.5.2.7.1
Cyclic Redundancy Check (CRC) Checksum
9.5.2.7.2
Exclusive or (XOR) Checksum
9.5.3
Control via Software
9.5.3.1
Startup Procedures
9.5.3.2
Shutdown Procedures
9.5.3.3
Protection and Monitoring
9.5.3.3.1
Overcurrent Shutdown (OCSD)
9.5.3.3.2
DC Detect
9.6
Register Maps
9.6.1
CONTROL PORT Registers
9.6.1.1
RESET_CTRL Register (Offset = 1h) [reset = 0x00]
Table 7.
RESET_CTRL Register Field Descriptions
9.6.1.2
DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
Table 8.
DEVICE_CTRL_1 Register Field Descriptions
9.6.1.3
DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]
Table 9.
DEVICE_CTRL_2 Register Field Descriptions
9.6.1.4
I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
Table 10.
I2C_PAGE_AUTO_INC Register Field Descriptions
9.6.1.5
SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
Table 11.
SIG_CH_CTRL Register Field Descriptions
9.6.1.6
CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
Table 12.
CLOCK_DET_CTRL Register Field Descriptions
9.6.1.7
SDOUT_SEL Register (Offset = 30h) [reset = 0h]
Table 13.
SDOUT_SEL Register Field Descriptions
9.6.1.8
I2S_CTRL Register (Offset = 31h) [reset = 0x00]
Table 14.
I2S_CTRL Register Field Descriptions
9.6.1.9
SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
Table 15.
SAP_CTRL1 Register Field Descriptions
9.6.1.10
SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
Table 16.
SAP_CTRL2 Register Field Descriptions
9.6.1.11
SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
Table 17.
SAP_CTRL3 Register Field Descriptions
9.6.1.12
FS_MON Register (Offset = 37h) [reset = 0x00]
Table 18.
FS_MON Register Field Descriptions
9.6.1.13
BCK_MON Register (Offset = 38h) [reset = 0x00]
Table 19.
BCK_MON Register Field Descriptions
9.6.1.14
CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
Table 20.
CLKDET_STATUS Register Field Descriptions
9.6.1.15
CHANNEL_FORCE_HIZ Register (Offset = 40h) [reset = 0x01]
Table 21.
CHANNEL_FORCE_HIZ Register Field Descriptions
9.6.1.16
DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]
Table 22.
DIG_VOL_CTR Register Field Descriptions
9.6.1.17
DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]
Table 23.
DIG_VOL_CTRL2 Register Field Descriptions
9.6.1.18
DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
Table 24.
DIG_VOL_CTRL3 Register Field Descriptions
9.6.1.19
AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
Table 25.
AUTO_MUTE_CTRL Register Field Descriptions
9.6.1.20
AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
Table 26.
AUTO_MUTE_TIME Register Field Descriptions
9.6.1.21
ANA_CTRL Register (Offset = 53h) [reset = 0x00]
Table 27.
ANA_CTRL Register Field Descriptions
9.6.1.22
AGAIN Register (Offset = 54h) [reset = 0x00]
Table 28.
AGAIN Register Field Descriptions
9.6.1.23
BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
Table 29.
BQ_WR_CTRL1 Register Field Descriptions
9.6.1.24
DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
Table 30.
DAC_CTRL Register Field Descriptions
9.6.1.25
ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]
Table 31.
ADR_PIN_CTRL Register Field Descriptions
9.6.1.26
ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]
Table 32.
ADR_PIN_CONFIG Register Field Descriptions
9.6.1.27
DSP_MISC Register (Offset = 66h) [reset = 0h]
Table 33.
DSP_MISC Register Field Descriptions
9.6.1.28
DIE_ID Register (Offset = 67h) [reset = 0h]
Table 34.
DIE_ID Register Field Descriptions
9.6.1.29
POWER_STATE Register (Offset = 68h) [reset = 0x00]
Table 35.
POWER_STATE Register Field Descriptions
9.6.1.30
AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
Table 36.
AUTOMUTE_STATE Register Field Descriptions
9.6.1.31
PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]
Table 37.
PHASE_CTR Register Field Descriptions
9.6.1.32
SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
Table 38.
SS_CTRL0 Register Field Descriptions
9.6.1.33
SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
Table 39.
SS_CTRL1 Register Field Descriptions
9.6.1.34
SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]
Table 40.
SS_CTRL2 Register Field Descriptions
9.6.1.35
SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
Table 41.
SS_CTRL3 Register Field Descriptions
9.6.1.36
SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
Table 42.
SS_CTRL4 Register Field Descriptions
9.6.1.37
CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
Table 43.
CHAN_FAULT Register Field Descriptions
9.6.1.38
GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
Table 44.
GLOBAL_FAULT1 Register Field Descriptions
9.6.1.39
GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
Table 45.
GLOBAL_FAULT2 Register Field Descriptions
9.6.1.40
OT WARNING Register (Offset = 73h) [reset = 0x00]
Table 46.
OT_WARNING Register Field Descriptions
9.6.1.41
PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
Table 47.
PIN_CONTROL1 Register Field Descriptions
9.6.1.42
PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
Table 48.
PIN_CONTROL2 Register Field Descriptions
9.6.1.43
MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
Table 49.
MISC_CONTROL Register Field Descriptions
9.6.1.44
HP_CONTROL Register (Offset = 77h) [reset = 0x00]
Table 50.
HP_CONTROL Register Field Descriptions
9.6.1.45
FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
Table 51.
FAULT_CLEAR Register Field Descriptions
10
Application and Implementation
10.1
Application Information
10.1.1
Bootstrap Capacitors
10.1.2
Inductor Selections
10.1.3
Power Supply Decoupling
10.1.4
Output EMI Filtering
10.2
Typical Applications
10.2.1
2.0 (Stereo BTL) System
10.2.2
Design Requirements
10.2.3
Detailed Design Procedure
10.2.3.1
Step 1: Hardware Integration
10.2.3.2
Step2: Speaker Tuning
10.2.3.3
Software Integration
10.2.4
Application Curves
10.2.5
Mono (PBTL) system
10.2.6
Application Curves
11
Power Supply Recommendations
11.1
DVDD Supply
11.2
PVDD Supply
12
Layout
12.1
Layout Guidelines
12.1.1
General Guidelines for Audio Amplifiers
12.1.2
Importance of PVDD Bypass Capacitor Placement on PVDD Network
12.1.3
Optimizing Thermal Performance
12.1.3.1
Device, Copper, and Component Layout
12.1.3.2
Stencil Pattern
12.1.3.2.1
PCB footprint and Via Arrangement
12.1.3.2.2
Solder Stencil
12.2
Layout Example
13
器件和文档支持
13.1
器件支持
13.1.1
器件命名规则
13.1.2
开发支持
13.2
接收文档更新通知
13.3
社区资源
13.4
商标
13.5
静电放电警告
13.6
Glossary
14
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
DCP|38
MPDS520B
散热焊盘机械数据 (封装 | 引脚)
DCP|38
PPTD170A
订购信息
zhcsjt7_oa
zhcsjt7_pm
1
特性
支持多路输出配置:
2.0 模式(8Ω、21V、THD+N=1%)下可提供 2 × 23W 的功率
单声道模式(4Ω、21V、THD+N=1%)下可提供 45W 的功率
优异的音频性能
1W、1kHz、PVDD = 12V 的条件下,THD+N ≤ 0.03%
SNR ≥ 107dB(A 加权),噪声级别 < 40µVrms
灵活的电源配置
PVDD:4.5V 至 26.4V
DVDD 和 I/O:1.8V 或 3.3V
灵活的音频 I/O
I
2
S、LJ、RJ、TDM、3 线数字音频接口(无需 MCLK)
支持 32、44.1、48、88.2、96kHz 采样率
用于音频监控、子通道或回声消除的 SDOUT
增强的音频处理能力
多频带高级 DRC 和 AGL
2×15 个 BQ、热折返、直流阻断
输入混合器、输出交叉开关、电平计
5 个 BQ + 单频带 DRC + THD 管理器(用于低音炮通道)
声场定位器选项
集成式自保护功能
邻近的引脚对引脚短路且无损坏
过流错误
过温警告和错误
欠压、过压锁定(UVLO、OVLO)
可轻松进行系统集成
I
2
C 软件控制
解决方案尺寸更小
与开环器件相比,所需的无源器件更少
对于 PVDD ≤ 14V 的大多数情况,可实现无电感器运行(铁氧体磁珠)
立体声耳机和立体声线路驱动器通过 I
2
C 调节增益
DirectPath 技术不再需要大容量的隔直电容器