ZHCSFX6C March   2016  – May 2017 TAS5753MD

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Speaker Amplifier Characteristics in All Modes
    7. 6.7  Speaker Amplifier Characteristics in Stereo Bridge Tied Load (BTL) Mode
    8. 6.8  Speaker Amplifier Characteristics in Stereo Post-Filter Parallel Bridge Tied Load (Post-Filter PBTL) Mode
    9. 6.9  Headphone Amplifier and Line Driver Characteristics
    10. 6.10 Protection Circuitry Characteristics
    11. 6.11 I²C Interface Timing Requirements
    12. 6.12 Serial Audio Port Timing Requirements
    13. 6.13 Typical Electrical Power Consumption
    14. 6.14 Typical Characteristics
      1. 6.14.1 Typical Characteristics - BTL Mode
      2. 6.14.2 Typical Characteristics - PBTL Mode
      3. 6.14.3 Typical Characteristics - Headphone Amplifier
      4. 6.14.4 Typical Characteristics - Line Driver
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Audio Signal Processing Overview
    4. 7.4 Feature Description
      1. 7.4.1 Clock, Autodetection, and PLL
      2. 7.4.2 PWM Section
      3. 7.4.3 PWM Level Meter
      4. 7.4.4 Automatic Gain Limiter (AGL)
      5. 7.4.5 Headphone/Line Amplifier
      6. 7.4.6 Fault Indication
      7. 7.4.7 SSTIMER Pin Functionality
      8. 7.4.8 Device Protection System
        1. 7.4.8.1 Overcurrent (OC) Protection With Current Limiting
        2. 7.4.8.2 Overtemperature Protection
        3. 7.4.8.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Serial Audio Port Operating Modes
      2. 7.5.2 Communication Port Operating Modes
      3. 7.5.3 Speaker Amplifier Modes
        1. 7.5.3.1 Stereo Mode
        2. 7.5.3.2 Mono Mode
    6. 7.6 Programming
      1. 7.6.1 I²C Serial Control Interface
        1. 7.6.1.1 General I²C Operation
        2. 7.6.1.2 I²C Slave Address
          1. 7.6.1.2.1 I²C Device Address Change Procedure
        3. 7.6.1.3 Single- and Multiple-Byte Transfers
        4. 7.6.1.4 Single-Byte Write
        5. 7.6.1.5 Multiple-Byte Write
        6. 7.6.1.6 Single-Byte Read
        7. 7.6.1.7 Multiple-Byte Read
      2. 7.6.2 Serial Interface Control and Timing
        1. 7.6.2.1 Serial Data Interface
        2. 7.6.2.2 I²S Timing
        3. 7.6.2.3 Left-Justified
        4. 7.6.2.4 Right-Justified
      3. 7.6.3 26-Bit 3.23 Number Format
    7. 7.7 Register Maps
      1. 7.7.1 Register Summary
      2. 7.7.2 Detailed Register Descriptions
        1. 7.7.2.1  Clock Control Register (0x00)
        2. 7.7.2.2  Device ID Register (0x01)
        3. 7.7.2.3  Error Status Register (0x02)
        4. 7.7.2.4  System Control Register 1 (0x03)
        5. 7.7.2.5  Serial Data Interface Register (0x04)
        6. 7.7.2.6  System Control Register 2 (0x05)
        7. 7.7.2.7  Soft Mute Register (0x06)
        8. 7.7.2.8  Volume Registers (0x07, 0x08, 0x09)
        9. 7.7.2.9  Volume Configuration Register (0x0E)
        10. 7.7.2.10 Modulation Limit Register (0x10)
        11. 7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. 7.7.2.12 PWM Shutdown Group Register (0x19)
        13. 7.7.2.13 Start/Stop Period Register (0x1A)
        14. 7.7.2.14 Oscillator Trim Register (0x1B)
        15. 7.7.2.15 BKND_ERR Register (0x1C)
        16. 7.7.2.16 Input Multiplexer Register (0x20)
        17. 7.7.2.17 PWM Output MUX Register (0x25)
        18. 7.7.2.18 AGL Control Register (0x46)
        19. 7.7.2.19 PWM Switching Rate Control Register (0x4F)
        20. 7.7.2.20 Bank Switch and EQ Control (0x50)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
        1. 8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
        2. 8.1.1.2 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Bridge Tied Load Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Component Selection and Hardware Connections
          2. 8.2.1.2.2 Control and Software Integration
          3. 8.2.1.2.3 I²C Pullup Resistors
          4. 8.2.1.2.4 Digital I/O Connectivity
          5. 8.2.1.2.5 Recommended Startup and Shutdown Procedures
            1. 8.2.1.2.5.1 Start-Up Sequence
            2. 8.2.1.2.5.2 Normal Operation
            3. 8.2.1.2.5.3 Shutdown Sequence
            4. 8.2.1.2.5.4 Power-Down Sequence
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Mono Parallel Bridge Tied Load Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 Stereo BTL Configuration with Headphone and Line Driver Amplifier Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Performance Plots
      4. 8.2.4 Mono Parallel Bridge-Tied Load Configuration with Headphone and Line Driver Amplifier
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Decoupling Capacitors
      2. 10.1.2 Thermal Performance and Grounding
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary

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订购信息

5 Pin Configuration and Functions

DCA Package
48-Pin HTSSOP With PowerPAD™
Top View
TAS5753MD PO_TAS5729xD_48DCA.gif

Pin Functions

PIN TYPE(1) TERMINATION DESCRIPTION
NAME NUMBER
ADR/SPK_FAULT 20 DI/DO — Dual-function pin which sets the LSB of the 7-bit I2C address to 0 if pulled to GND, 1 if pulled to DVDD. If configured to be a fault output via the System Control Register 2 (0x05), the pin is pulled low when an internal fault with the speaker amplifier occurs. A pullup or pulldown resistor is required, as is shown in the .
AGND 36 P — Ground for analog circuitry(3)
AVDD 19 P — Power supply for internal analog circuitry
ANA_REG1 18 P — Linear voltage regulator output derived from AVDD supply which is used for internal analog circuitry. Nominal 1.8-V output.(2)
ANA_REG2 37 P — Linear voltage regulator output derived from AVDD supply which is used for internal analog circuitry. Nominal 3.3-V output.(2)
BSTRPx 3, 42, 46, 47 P — Connection points for the bootstrap capacitors which are used to create a power supply for the high-side gate drive of the device.
DGND 35 P — Ground for digital circuitry(3)
DIG_REG 24 P — Linear voltage regulator output derived from the DVDD supply which is used for internal digital circuitry.(2)
DR_CN 12 P — Negative pin for capacitor connection used in headphone amplifier and line driver charge pump
DR_CP 13 P — Positive pin for capacitor connection used in headphone amplifier and line driver charge pump
DR_INx 7, 10 AI — Input for channel A or B of headphone amplifier or line driver
DR_OUTx 8, 9 AO — Output for channel A or B of headphone amplifier or line driver
DR_SDI 39 DI — Places the headphone amplifier/line driver in shutdown when pulled low.
DRVSS 11 P — Negative supply generated by charge pump for ground centered headphone and line driver output
DRVDD 14 P — Power supply for internal headphone and line driver circuitry
DVDD 34 P — Power supply for the internal digital circuitry
GVDD_REG 40 P — Voltage regulator derived from PVDD supply(2)
LRCLK 26 DI Pulldown Word select clock of the serial audio port.
MCLK 21 DI Pulldown Master clock used for internal clock tree and sub-circuit and state machine clocking
NC 31 — — Not connected inside the device (all NC terminals should be connected to ground for optimal thermal performance)
OSC_GND 23 P — Ground for oscillator circuitry (the terminal should be connected to the system ground)
OSC_RES 22 AO — Connection point for oscillator trim resistor
PDN 25 DI Pullup Quick powerdown of the device that is used upon an unexpected loss of the PVDD or DVDD power supply to quickly transition the outputs of the speaker amplifier to Hi-Z. The quick powerdown feature avoids the audible anamolies that would occur as a result of loss of either of the supplies.
PGND 1, 44 P — Ground for power device circuitry(3)
PLL_FLTM 16 AI/AO — Negative connection point for the PLL loop filter components
PLL_FLTP 17 AI/AO — Positive connection point for the PLL loop filter components
PLL_GND 15 P — Ground for PLL circuitry (this terminal should be connected to the system ground)
PowerPAD™ — P — Thermal and ground pad that provides both an electrical connection to the ground plane and a thermal path to the PCB for heat dissipation. The pad must be grounded to the system ground. (3)
PVDD 4, 41 P — Power supply for internal power circuitry
RST 32 DI Pullup Places the device in reset when pulled low
SCL 30 DI — I2C serial control port clock
SCLK 27 DI Pulldown Bit clock of the serial audio port
SDA 29 DI/DO — I2C serial control port data
SDIN 28 DI Pulldown Data line to the serial data port
SPK_OUTx 2, 43, 45, 48 AO — Speaker amplifier outputs
SSTIMER 38 AI — Controls ramp time of SPK_OUTx to minimize pop. Leave the pin floating for BD mode. Requires capacitor to GND in AD mode, as is shown in . The capacitor determines the ramp time.
TEST1/TEST2 5/6 DO — Used for testing during device production (the terminal must be left floating)
TEST3 33 DI — Used for testing during device production (the terminal must be connected to GND)
(1) TYPE: AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0 V)
(2) This pin is provided as a connection point for filtering capacitors for the supply and must not be used to power any external circuitry.
(3) This pin should be connected to the system ground.