ZHCS929A May   2012  – March 2015 TAS5622A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Specification Stereo (BTL)
    7. 6.7 Audio Specification 4 Channels (SE)
    8. 6.8 Audio Specification Mono (PBTL)
    9. 6.9 Typical Characteristics
      1. 6.9.1 Typical Characteristics, BTL Configuration
      2. 6.9.2 Typical Characteristics, SE Configuration
      3. 6.9.3 Typical Characteristics, PBTL Configuration
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  System Power-Up and Power-Down Sequence
        1. 7.3.1.1 Powering Up
        2. 7.3.1.2 Powering Down
      2. 7.3.2  Start-up and Shutdown Ramp Sequence
      3. 7.3.3  Unused Output Channels
      4. 7.3.4  Device Protection System
      5. 7.3.5  Pin-to-Pin Short Circuit Protection (PPSC)
      6. 7.3.6  Overtemperature Protection
      7. 7.3.7  Overtemperature Warning, OTW
      8. 7.3.8  Undervoltage Protection (UVP) and Power-On Reset (POR)
      9. 7.3.9  Error Reporting
      10. 7.3.10 Fault Handling
      11. 7.3.11 Device Reset
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical BTL Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical SE Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Typical PBTL Configuration
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Boot Strap Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material Recommendation
      2. 10.1.2 PVDD Capacitor Recommendation
      3. 10.1.3 Decoupling Capacitor Recommendation
      4. 10.1.4 Circuit Component Requirements
      5. 10.1.5 Printed Circuit Board Requirements
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DDV Package
44-Pin HTSSOP
Top View
TAS5622A po2_DDV_las813.gif

Pin Functions

PIN I/O/P(1) DESCRIPTION
NAME NO.
AVDD 13 P Internal voltage regulator, analog section
BST_A 44 P Bootstrap pin, A-side
BST_B 43 P Bootstrap pin, B-side
BST_C 24 P Bootstrap pin, C-side
BST_D 23 P Bootstrap pin, D-side
CLIP 18 O Clipping warning; open drain; active low
C_START 7 O Start-up ramp
DVDD 8 P Internal voltage regulator, digital section
FAULT 16 O Shutdown signal, open drain; active low
GND 9, 10, 11, 12, 25,
26, 33, 34, 41, 42		 P Ground
GVDD_AB 1 P Gate-drive voltage supply; AB-side
GVDD_CD 22 P Gate-drive voltage supply; CD-side
INPUT_A 5 I PWM Input signal for half-bridge A
INPUT_B 6 I PWM Input signal for half-bridge B
INPUT_C 14 I PWM Input signal for half-bridge C
INPUT_D 15 I PWM Input signal for half-bridge D
M1 19 I Mode selection 1 (LSB)
M2 20 I Mode selection 2
M3 21 I Mode selection 3 (MSB)
OC_ADJ 3 O Over-Current threshold programming pin
OTW 17 O Over-temperature warning; open drain; active low
OUT_A 39, 40 O Output, half-bridge A
OUT_B 35 O Output, half-bridge B
OUT_C 32 O Output, half-bridge C
OUT_D 27, 28 O Output, half-bridge D
PVDD_AB 36, 37, 38 P PVDD supply for half-bridge A and B
PVDD_CD 29, 30, 31 P PVDD supply for half-bridge C and D
RESET 4 I Device reset Input; active low
VDD 2 P Input power supply
PowerPAD™ – P Ground, connect to grounded heat sink
(1) I = Input, O = Output, P = Power

Mode Selection Pins

MODE PINS PWM INPUT(1) OUTPUT CONFIGURATION INPUT A INPUT B INPUT C INPUT D MODE
M3 M2 M1
0 0 0 2N + 1 2 x BTL PWMa PWMb PWMc PWMd AD mode
0 0 1 1N + 1(2) 2 x BTL PWMa Unused PWMc Unused AD mode
0 1 0 2N + 1 2 x BTL PWMa PWMb PWMc PWMd BD mode
0 1 1 1N + 1(2) 1 x BTL + 2 x SE PWMa Unused PWMc PWMd AD mode
1 0 0 2N + 1 1 x PBTL PWMa PWMb 0 0 AD mode
1 0 0 1N + 1(2) 1 x PBTL PWMa Unused 0 1 AD mode
1 0 0 2N + 1 1 x PBTL PWMa PWMb 1 0 BD mode
1 0 1 1N + 1 4 x SE(3) PWMa PWMb PWMc PWMd AD mode
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.
(3) The 4xSE mode can be used as 1xBTL + 2xSE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for improved DC offset accuracy