ZHCSFY2B August   2015  – February 2019 TAS2555

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  I2C Timing Requirements
    7. 7.7  SPI Timing Requirements
    8. 7.8  I2S/LJF/RJF Timing in Master Mode
    9. 7.9  I2S/LJF/RJF Timing in Slave Mode
    10. 7.10 DSP Timing in Master Mode
    11. 7.11 DSP Timing in Slave Mode
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  General I2C Operation
      2. 9.3.2  Single-Byte and Multiple-Byte Transfers
      3. 9.3.3  Single-Byte Write
      4. 9.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.3.5  Single-Byte Read
      6. 9.3.6  Multiple-Byte Read
      7. 9.3.7  General SPI Operation
      8. 9.3.8  Class-D Edge Rate Control
      9. 9.3.9  Battery Tracking AGC
      10. 9.3.10 Configurable Boost Current Limit (ILIM)
        1. 9.3.10.1 Fault Protection
          1. 9.3.10.1.1 OverCurrent
          2. 9.3.10.1.2 Analog Undervoltage
          3. 9.3.10.1.3 Overtemperature
          4. 9.3.10.1.4 Clocking Faults
        2. 9.3.10.2 Brownout
        3. 9.3.10.3 Spread Spectrum vs Synchronized
        4. 9.3.10.4 IRQs and Flags
        5. 9.3.10.5 Software Reset
        6. 9.3.10.6 PurePath Console 3 Software TAS2555 Application
    4. 9.4 Device Functional Modes
      1. 9.4.1 Audio Digital I/O Interface
        1. 9.4.1.1 Right-Justified Mode (RJF)
        2. 9.4.1.2 Left-Justified Mode (LJF)
        3. 9.4.1.3 I2S Mode
        4. 9.4.1.4 DSP Mode
      2. 9.4.2 TDM Mode
      3. 9.4.3 Device Digital Processing Modes
        1. 9.4.3.1 ROM Mode 1
        2. 9.4.3.2 ROM Mode 2
        3. 9.4.3.3 SmartAmp Mode
      4. 9.4.4 Low Power Sleep Mode
    5. 9.5 Programming
      1. 9.5.1 Code Loading and CRC check
      2. 9.5.2 Device Power Up, Power Down, Mute and Un-mute Sequence
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Detailed Design Procedure
          1. 10.2.1.1.1 Mono/Stereo Configuration
          2. 10.2.1.1.2 Boost Converter Passive Devices
          3. 10.2.1.1.3 EMI Passive Devices
          4. 10.2.1.1.4 Miscellaneous Passive Devices
      2. 10.2.2 Application Performance Plots
    3. 10.3 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Power Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Register Map
    1. 13.1 Register Map Summary
    2. 13.2 Book 0 Page 0
      1. 13.2.1  Book 0 / Page 0 / Register 0: Page Select Register - 0x00 / 0x00 / 0x00 (B0_P0_R0)
      2. 13.2.2  Book 0 / Page 0 / Register 1: Software Reset Register - 0x00 / 0x00 / 0x01 (B0_P0_R1)
      3. 13.2.3  Book 0 / Page 0 / Register 2-3: Reserved Registers - 0x00 / 0x00 / 0x02-0x03 (B0_P0_R2-3)
      4. 13.2.4  Book 0 / Page 0 / Register 4: Power Control Register - 0x00 / 0x00 / 0x04 (B0_P0_R4)
      5. 13.2.5  Book 0 / Page 0 / Register 5: Power Control Register 2 - 0x00 / 0x00 / 0x05 (B0_P0_R5)
      6. 13.2.6  Book 0 / Page 0 / Register 6: Speaker Control Register - 0x00 / 0x00 / 0x06 (B0_P0_R6)
      7. 13.2.7  Book 0 / Page 0 / Register 7: Mute Register - 0x00 / 0x00 / 0x07 (B0_P0_R7)
      8. 13.2.8  Book 0 / Page 0 / Register 8: Channel Control Register - 0x00 / 0x00 / 0x08 (B0_P0_R8)
      9. 13.2.9  Book 0 / Page 0 / Register 9-31: Reserved Registers - 0x00 / 0x00 / 0x09-0x1F (B0_P0_R9-31)
      10. 13.2.10 Book 0 / Page 0 / Register 32: CRC Checksum Register - 0x00 / 0x00 / 0x20 (B0_P0_R32)
      11. 13.2.11 Book 0 / Page 0 / Register 33: Checksum Reset Register - 0x00 / 0x00 / 0x21 (B0_P0_R33)
      12. 13.2.12 Book 0 / Page 0 / Register 34: Device DSP Mode Register - 0x00 / 0x00 / 0x22 (B0_P0_R34)
      13. 13.2.13 Book 0 / Page 0 / Register 35-39: Reserved Registers - 0x00 / 0x00 / 0x23-0x27 (B0_P0_R35-R39)
      14. 13.2.14 Book 0 / Page 0 / Register 40: Class-D SSM Mode Register - 0x00 / 0x00 / 0x28 (B0_P0_R40)
      15. 13.2.15 Book 0 / Page 0 / Register 41: Reserved Registers - 0x00 / 0x00 / 0x29 (B0_P0_R41)
      16. 13.2.16 Book 0 / Page 0 / Register 42: Digital Playback Control Register - 0x00 / 0x00 / 0x2A (B0_P0_R42)
      17. 13.2.17 Book 0 / Page 0 / Register 43: Current Limit Register - 0x00 / 0x00 / 0x2B (B0_P0_R43)
      18. 13.2.18 Book 0 / Page 0 / Register 44: Clock Error Control 1 Register - 0x00 / 0x00 / 0x2C (B0_P0_R44)
      19. 13.2.19 Book 0 / Page 0 / Register 45: Clock Error Control 2 Register - 0x00 / 0x00 / 0x2D (B0_P0_R45)
      20. 13.2.20 Book 0 / Page 0 / Register 46: Clock Error Control 3 Register - 0x00 / 0x00 / 0x2E (B0_P0_R46)
      21. 13.2.21 Book 0 / Page 0 / Register 47-99: Reserved Registers - 0x00 / 0x00 / 0x2F-0x63 (B0_P0_R47-R99)
      22. 13.2.22 Book 0 / Page 0 / Register 100: Power Up Flag Register - 0x00 / 0x00 / 0x64 (B0_P0_R100)
      23. 13.2.23 Book 0 / Page 0 / Register 101-103: Reserved Registers - 0x00 / 0x00 / 0x65-0x67 (B0_P0_R101-R103)
      24. 13.2.24 Book 0 / Page 0 / Register 104: Interrupt Flags DAC & OCP/OTP Sticky Register - 0x00 / 0x00 / 0x68 (B0_P0_R104)
      25. 13.2.25 Book 0 / Page 0 / Register 105-107: Reserved Registers - 0x00 / 0x00 / 0x69-0x6B (B0_P0_R105-R107)
      26. 13.2.26 Book 0 / Page 0 / Register 108: DSP Interrupt Output Sticky Register - 0x00 / 0x00 / 0x6C (B0_P0_R108)
      27. 13.2.27 Book 0 / Page 0 / Register 109-120: Reserved Registers - 0x00 / 0x00 / 0x6D-0x78 (B0_P0_R109-R120)
      28. 13.2.28 Book 0 / Page 0 / Register 121: Power Modes Register - 0x00 / 0x00 / 0x79 (B0_P0_R121)
      29. 13.2.29 Book 0 / Page 0 / Register 122-126: Reserved Registers - 0x00 / 0x00 / 0x7A-0x7E (B0_P0_R122-R126)
      30. 13.2.30 Book 0 / Page 0 / Register 127: Book Selection Register - 0x00 / 0x00 / 0x7F (B0_P0_R127)
    3. 13.3 Book 0 Page 1
      1. 13.3.1  Book 0 / Page 1 / Register 0: Page Select Register - 0x00 / 0x01 / 0x00 (B0_P1_R0)
      2. 13.3.2  Book 0 / Page 1 / Register 1: ASI1 DAC Format Register - 0x00 / 0x01 / 0x01 (B0_P1_R1)
      3. 13.3.3  Book 0 / Page 1 / Register 2: ASI1 ADC Format Register - 0x00 / 0x01 / 0x02 (B0_P1_R2)
      4. 13.3.4  Book 0 / Page 1 / Register 3: ASI1 Offset Register - 0x00 / 0x00 / 0x03 (B0_P1_R3)
      5. 13.3.5  Book 0 / Page 1 / Register 4-6: Reserved Registers - 0x00 / 0x01 / 0x04-0x06 (B0_P1_R4-6)
      6. 13.3.6  Book 0 / Page 1 / Register 7: ASI1 ADC Path Register - 0x00 / 0x01 / 0x07 (B0_P1_R7)
      7. 13.3.7  Book 0 / Page 1 / Register 8: ASI1 DAC BCLK Register - 0x00 / 0x01 / 0x08 (B0_P1_R8)
      8. 13.3.8  Book 0 / Page 1 / Register 9: ASI1 DAC WCLK Register - 0x00 / 0x01 / 0x09 (B0_P1_R9)
      9. 13.3.9  Book 0 / Page 1 / Register 10: ASI1 ADC BCLK Register - 0x00 / 0x01 / 0x0A (B0_P1_R10)
      10. 13.3.10 Book 0 / Page 1 / Register 11: ASI1 ADC WCLK Register - 0x00 / 0x01 / 0x0B (B0_P1_R11)
      11. 13.3.11 Book 0 / Page 1 / Register 12: ASI1 DIN/DOUT MUX Register - 0x00 / 0x01 / 0x0C (B0_P1_R12)
      12. 13.3.12 Book 0 / Page 1 / Register 13: ASI1 BDIV Clock Select Register - 0x00 / 0x01 / 0x0D (B0_P1_R13)
      13. 13.3.13 Book 0 / Page 1 / Register 14: ASI1 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x0E (B0_P1_R14)
      14. 13.3.14 Book 0 / Page 1 / Register 15: ASI1 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x0F (B0_P1_R15)
      15. 13.3.15 Book 0 / Page 1 / Register 16: ASI1 DAC Clock Output Register - 0x00 / 0x01 / 0x10 (B0_P1_R16)
      16. 13.3.16 Book 0 / Page 1 / Register 17: ASI1 ADC Clock Output Register - 0x00 / 0x01 / 0x11 (B0_P1_R17)
      17. 13.3.17 Book 0 / Page 1 / Register 18-20: Reserved Registers - 0x00 / 0x01 / 0x12-0x14 (B0_P1_R18-20)
      18. 13.3.18 Book 0 / Page 1 / Register 21: ASI2 DAC Format Register - 0x00 / 0x01 / 0x15 (B0_P1_R21)
      19. 13.3.19 Book 0 / Page 1 / Register 22: ASI2 ADC Format Register - 0x00 / 0x01 / 0x16 (B0_P1_R22)
      20. 13.3.20 Book 0 / Page 1 / Register 23: ASI2 Offset Register - 0x00 / 0x01 / 0x17 (B0_P1_R23)
      21. 13.3.21 Book 0 / Page 1 / Register 24-26: Reserved Registers - 0x00 / 0x01 / 0x18-0x1A (B0_P1_R24-26)
      22. 13.3.22 Book 0 / Page 1 / Register 27: ASI2 ADC Path Register - 0x00 / 0x01 / 0x1B (B0_P1_R27)
      23. 13.3.23 Book 0 / Page 1 / Register 28: ASI2 DAC BCLK Register - 0x00 / 0x01 / 0x1C (B0_P1_R28)
      24. 13.3.24 Book 0 / Page 1 / Register 29: ASI2 DAC WCLK Register - 0x00 / 0x01 / 0x1D (B0_P1_R29)
      25. 13.3.25 Book 0 / Page 1 / Register 30: ASI2 ADC BCLK Register - 0x00 / 0x01 / 0x1E (B0_P1_R30)
      26. 13.3.26 Book 0 / Page 1 / Register 31: ASI2 ADC WCLK Register - 0x00 / 0x01 / 0x1F (B0_P1_R31)
      27. 13.3.27 Book 0 / Page 1 / Register 32: ASI2 DIN/DOUT MUX - 0x00 / 0x01 / 0x20 (B0_P1_R32)
      28. 13.3.28 Book 0 / Page 1 / Register 33: ASI2 BDIV Clock Select Register - 0x00 / 0x01 / 0x21 (B0_P1_R33)
      29. 13.3.29 Book 0 / Page 1 / Register 34: ASI2 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x22 (B0_P1_R34)
      30. 13.3.30 Book 0 / Page 1 / Register 35: ASI2 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x23 (B0_P1_R35)
      31. 13.3.31 Book 0 / Page 1 / Register 36: ASI2 DAC Clock Output Register - 0x00 / 0x01 / 0x24 (B0_P1_R36)
      32. 13.3.32 Book 0 / Page 1 / Register 37: ASI2 ADC Clock Output Register - 0x00 / 0x01 / 0x25 (B0_P1_R37)
      33. 13.3.33 Book 0 / Page 1 / Register 38-60: Reserved Registers - 0x00 / 0x01 / 0x26-0x3C (B0_P1_R38-60)
      34. 13.3.34 Book 0 / Page 1 / Register 61: BCLK1_GPIO1 Pin Register - 0x00 / 0x01 / 0x3D (B0_P1_R61)
      35. 13.3.35 Book 0 / Page 1 / Register 62: WCLK1_GPIO2 Pin Register - 0x00 / 0x01 / 0x3E (B0_P1_R62)
      36. 13.3.36 Book 0 / Page 1 / Register 63: DOUT1_GPIO3 Pin Register - 0x00 / 0x01 / 0x3F (B0_P1_R63)
      37. 13.3.37 Book 0 / Page 1 / Register 64: IRQ_GPIO4 Pin Register - 0x00 / 0x01 / 0x40 (B0_P1_R64)
      38. 13.3.38 Book 0 / Page 1 / Register 65: BCLK2_GPIO5 Pin Register - 0x00 / 0x01 / 0x41 (B0_P1_R65)
      39. 13.3.39 Book 0 / Page 1 / Register 66: WCLK2_GPIO6 Pin Register - 0x00 / 0x01 / 0x42 (B0_P1_R66)
      40. 13.3.40 Book 0 / Page 1 / Register 67: DOUT2_GPIO7 Pin Register - 0x00 / 0x01 / 0x43 (B0_P1_R67)
      41. 13.3.41 Book 0 / Page 1 / Register 68: DIN2_GPIO8 Pin Register - 0x00 / 0x01 / 0x44 (B0_P1_R68)
      42. 13.3.42 Book 0 / Page 1 / Register 69: ICC_GPIO9 Pin(ICC_CLK) Register - 0x00 / 0x01 / 0x45 (B0_P1_R69)
      43. 13.3.43 Book 0 / Page 1 / Register 70: ICC_GPIO10 Pin Register - 0x00 / 0x01 / 0x46 (B0_P1_R70)
      44. 13.3.44 Book 0 / Page 1 / Register 71-76: Reserved Registers - 0x00 / 0x01 / 0x47-0x4C (B0_P1_R71-76)
      45. 13.3.45 Book 0 / Page 1 / Register 77: GPI Pins Register - 0x00 / 0x01 / 0x4D (B0_P1_R77)
      46. 13.3.46 Book 0 / Page 1 / Register 78: Reserved Register - 0x00 / 0x01 / 0x4E (B0_P1_R78)
      47. 13.3.47 Book 0 / Page 1 / Register 79: GPIO HIZ CTRL1 Register - 0x00 / 0x01 / 0x4F (B0_P1_R79)
      48. 13.3.48 Book 0 / Page 1 / Register 80: GPIO HIZ CTRL2 Register - 0x00 / 0x01 / 0x50 (B0_P1_R80)
      49. 13.3.49 Book 0 / Page 1 / Register 81: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x51 (B0_P1_R81)
      50. 13.3.50 Book 0 / Page 1 / Register 82: GPIO HIZ CTRL4 Register - 0x00 / 0x01 / 0x52 (B0_P1_R82)
      51. 13.3.51 Book 0 / Page 1 / Register 83: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x53 (B0_P1_R83)
      52. 13.3.52 Book 0 / Page 1 / Register 84-86: Reserved Registers - 0x00 / 0x01 / 0x54-0x56 (B0_P1_R84-86)
      53. 13.3.53 Book 0 / Page 1 / Register 87: GPIO Pin 1 Register - 0x00 / 0x01 / 0x57 (B0_P1_R87)
      54. 13.3.54 Book 0 / Page 1 / Register 88: GPIO Pin 2 Register - 0x00 / 0x01 / 0x58 (B0_P1_R88)
      55. 13.3.55 Book 0 / Page 1 / Register 89: GPIO Pin 3 Register - 0x00 / 0x01 / 0x59 (B0_P1_R89)
      56. 13.3.56 Book 0 / Page 1 / Register 90-107: Reserved Registers - 0x00 / 0x01 / 0x5A-0x6B (B0_P1_R84-86)
      57. 13.3.57 Book 0 / Page 1 / Register 108: Interrupt Control 1 Register - 0x00 / 0x01 / 0x6C (B0_P1_R108)
      58. 13.3.58 Book 0 / Page 1 / Register 109: Interrupt Control 2 Register - 0x00 / 0x01 / 0x6D (B0_P1_R109)
      59. 13.3.59 Book 0 / Page 1 / Register 110: Interrupt Control 3 Register - 0x00 / 0x01 / 0x6E (B0_P1_R110)
      60. 13.3.60 Book 0 / Page 1 / Register 111: Interrupt Control 4 Register - 0x00 / 0x01 / 0x6F (B0_P1_R111)
      61. 13.3.61 Book 0 / Page 1 / Register 112: Interrupt Control 5 Register - 0x00 / 0x01 / 0x70 (B0_P1_R112)
      62. 13.3.62 Book 0 / Page 1 / Register 113: Interrupt Control 6 Register - 0x00 / 0x01 / 0x71 (B0_P1_R113)
      63. 13.3.63 Book 0 / Page 1 / Register 114-127: Reserved Register - 0x00 / 0x01 / 0x72-0x7F (B0_P1_R127)
    4. 13.4 Book 0 Page 2
      1. 13.4.1 Book 0 / Page 2 / Register 0: Page Select Register - 0x00 / 0x02 / 0x00 (B0_P0_R0)
      2. 13.4.2 Book 0 / Page 2 / Register 1-5: Reserved Register - 0x00 / 0x02 / 0x01-0x05 (B0_P1_R1-5)
      3. 13.4.3 Book 0 / Page 2 / Register 6: Ramp Generator Frequency Register - 0x00 / 0x02 / 0x06 (B0_P2_R6)
      4. 13.4.4 Book 0 / Page 2 / Register 7-23: Reserved Register - 0x00 / 0x02 / 0x07-0x17 (B0_P1_R7-23)
      5. 13.4.5 Book 0 / Page 2 / Register 24: Inrush Optimization 1 Register - 0x00 / 0x02 / 0x18 (B0_P2_R24)
      6. 13.4.6 Book 0 / Page 2 / Register 25: Inrush Optimization 2 Register - 0x00 / 0x02 / 0x19 (B0_P2_R25)
      7. 13.4.7 Book 0 / Page 2 / Register 26: Inrush Optimization 3 Register - 0x00 / 0x02 / 0x1A (B0_P2_R25)
      8. 13.4.8 Book 0 / Page 2 / Register 27: Inrush Optimization 4 Register - 0x00 / 0x02 / 0x1B (B0_P2_R25)
      9. 13.4.9 Book 0 / Page 2 / Register 28-127: Reserved Register - 0x00 / 0x02 / 0x1C-0x7F (B0_P1_R28-127)
    5. 13.5 Book 100 Page 0
      1. 13.5.1  Book 100 / Page 0 / Register 0: Page Select Register - 0x64 / 0x00 / 0x00 (B100_P0_R0)
      2. 13.5.2  Book 100 / Page 0 / Register 1: DAC Interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      3. 13.5.3  Book 100 / Page 0 / Register 2: ADC interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      4. 13.5.4  Book 100 / Page 0 / Register 3-6: Reserved Register - 0x64 / 0x00 / 0x03-0x06 (B100_P0_R3-6)
      5. 13.5.5  Book 100 / Page 0 / Register 7: DSP Mute Register - 0x64 / 0x00 / 0x07 (B100_P0_R7)
      6. 13.5.6  Book 100 / Page 0 / Register 8-15: Reserved Register - 0x64 / 0x00 / 0x08-0x0F (B100_P0_R8-15)
      7. 13.5.7  Book 100 / Page 0 / Register 16: Interrupt 1 DSP Register - 0x64 / 0x00 / 0x10 (B100_P0_R16)
      8. 13.5.8  Book 100 / Page 0/ Register 17: Interrupt 2 DSP Register - 0x64 / 0x00 / 0x11 (B100_P0_R17)
      9. 13.5.9  Book 100 / Page 0 / Register 18: Condition 1 DSP Register - 0x64 / 0x00 / 0x12 (B100_P0_R18)
      10. 13.5.10 Book 100/ Page 0 / Register 19: Condition 2 DSP Register - 0x64 / 0x00 / 0x13 (B100_P0_R19)
      11. 13.5.11 Book 100 / Page 0 / Register 20: ISR and COND Control Register - 0x64 / 0x00 / 0x14 (B100_P0_R20)
      12. 13.5.12 Book 100 / Page 0/ Register 21: DSP Control Register - 0x64 / 0x00 / 0x15 (B100_P0_R21)
      13. 13.5.13 Book 100 / Page 0 / Register 22-26: Reserved Register - 0x64 / 0x00 / 0x16-0x1A (B100_P0_R22-26)
      14. 13.5.14 Book 100 / Page 0 / Register 27:PLL CLKIN Divider Register - 0x64 / 0x00 / 0x1B (B100_P0_R27)
      15. 13.5.15 Book 100 / Page 0 / Register 28:PLL J-VAL Divider Register - 0x64 / 0x00 / 0x1C (B100_P0_R28)
      16. 13.5.16 Book 100 / Page 0 / Register 29:PLL D-VAL Divider 2 Register - 0x64 / 0x00 / 0x1D (B100_P0_R29)
      17. 13.5.17 Book 100 / Page 0 / Register 30:PLL D-VAL Divider 1 Register - 0x64 / 0x00 / 0x1E (B100_P0_R30)
      18. 13.5.18 Book 100 / Page 0 / Register 31:DSP Clock Register - 0x64 / 0x00 / 0x1F (B100_P0_R31)
      19. 13.5.19 Book 100 / Page 0 / Register 32: N-VAL Divider Register - 0x64 / 0x00 / 0x20 (B100_P0_R32)
      20. 13.5.20 Book 100 / Page 0 / Register 33: MDAC-VAL Divider Register - 0x64 / 0x00 / 0x21 (B100_P0_R33)
      21. 13.5.21 Book 100 / Page 0 / Register 34: MADC-VAL Divider Register - 0x64 / 0x00 / 0x22 (B100_P0_R34)
      22. 13.5.22 Book 100 / Page 0 / Register 35-37: Reserved Register - 0x64 / 0x00 / 0x23-0x25 (B100_P0_R35-37)
      23. 13.5.23 Book 100 / Page 0 / Register 38: Charge-pump Clock Register - 0x64 / 0x00 / 0x26 (B100_P0_R38)
      24. 13.5.24 Book 100 / Page 0 / Register 39: Boost Clock Register - 0x64 / 0x00 / 0x27 (B100_P0_R39)
      25. 13.5.25 Book 100 / Page 0 / Register 40: Ramp Clock 1 Register - 0x64 / 0x00 / 0x28 (B100_P0_R40)
      26. 13.5.26 Book 100 / Page 0 / Register 41-42: Reserved Register - 0x64 / 0x00 / 0x29-0x2A (B100_P0_R41-42)
      27. 13.5.27 Book 100 / Page 0 / Register 43: Ramp Clock 2 Register - 0x64 / 0x00 / 0x2B (B100_P0_R43)
      28. 13.5.28 Book 100 / Page 0 / Register 44: Ramp Clock 3 Register - 0x64 / 0x00 / 0x2C (B100_P0_R44)
      29. 13.5.29 Book 100 / Page 0/ Register 45-126: Reserved Register - 0x64 / 0x01 / 0x2D-0x7E (B100_P0_R45-126)
      30. 13.5.30 Book 100 / Page 0 / Register 127: Book Selection Register - 0x64 / 0x00 / 0x7F (B100_P0_R127)
  14. 14器件和文档支持
    1. 14.1 文档支持
    2. 14.2 社区资源
    3. 14.3 商标
    4. 14.4 静电放电警告
    5. 14.5 术语表
  15. 15机械、封装和可订购信息
    1. 15.1 封装尺寸

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YZ|42
散热焊盘机械数据 (封装 | 引脚)
订购信息

13.1 Register Map Summary

Table 6. Summary of Register Map

Decimal Hex DESCRIPTION
BOOK NO. PAGE NO. REG. NO. BOOK NO. PAGE NO. REG. NO.
0 0 0 0x00 0x00 0x00 Page Select
0 0 1 0x00 0x00 0x01 Software Reset
0 0 2-3 0x00 0x00 0x02-0x03 Reserved
0 0 4 0x00 0x00 0x04 Power Control
0 0 5 0x00 0x00 0x05 Power Control 2
0 0 6 0x00 0x00 0x06 Speaker Control
0 0 7 0x00 0x00 0x07 Mute
0 0 8 0x00 0x00 0x08 Channel Control
0 0 9-31 0x00 0x00 0x09-0x1F Reserved
0 0 32 0x00 0x00 0x20 CRC Checksum
0 0 33 0x00 0x00 0x21 Checksum Reset
0 0 34 0x00 0x00 0x22 Device DSP Mode
0 0 35-39 0x00 0x00 0x23-0x27 Reserved
0 0 40 0x00 0x00 0x28 Class-D SSM Mode
0 0 41 0x00 0x00 0x29 Reserved
0 0 42 0x00 0x00 0x2A Digital Playback Control
0 0 43 0x00 0x00 0x2B Current Limit
0 0 44 0x00 0x00 0x2C Clock Error Control 1
0 0 45 0x00 0x00 0x2D Clock Error Control 2
0 0 46 0x00 0x00 0x2E Clock Error Control 3
0 0 47-99 0x00 0x00 0x2F-0x63 Reserved
0 0 100 0x00 0x00 0x64 Power Up Flag
0 0 101-103 0x00 0x00 0x65-0x67 Reserved
0 0 104 0x00 0x00 0x68 Interrupt Flags DAC & OCP/OTP Sticky
0 0 105-107 0x00 0x00 0x69-0x6B Reserved
0 0 108 0x00 0x00 0x6C DSP Interrupt Output Sticky
0 0 109-120 0x00 0x00 0x6D-0x78 Reserved
0 0 121 0x00 0x00 0x79 Power Modes
0 0 122-126 0x00 0x00 0x7A-0x7E Reserved
0 0 127 0x00 0x00 0x7F Book Selection
0 1 0 0x00 0x01 0x00 Page Select
0 1 1 0x00 0x01 0x01 ASI1 DAC Format
0 1 2 0x00 0x01 0x02 ASI1 ADC Format
0 1 3 0x00 0x01 0x03 ASI1 Offset
0 1 4-6 0x00 0x01 0x04-0x06 Reserved
0 1 7 0x00 0x01 0x07 ASI1 ADC Path
0 1 8 0x00 0x01 0x08 ASI1 DAC BCLK
0 1 9 0x00 0x01 0x09 ASI1 DAC WCLK
0 1 10 0x00 0x01 0x0A ASI1 ADC BCLK
0 1 11 0x00 0x01 0x0B ASI1 ADC WCLK
0 1 12 0x00 0x01 0x0C ASI1 DIN/DOUT MUX
0 1 13 0x00 0x01 0x0D ASI1 BDIV Clock Select
0 1 14 0x00 0x01 0x0E ASI1 BDIV Clock Ratio
0 1 15 0x00 0x01 0x0F ASI1 WDIV Clock Ratio
0 1 16 0x00 0x01 0x10 ASI1 DAC Clock Output
0 1 17 0x00 0x01 0x11 ASI1 ADC Clock Output
0 1 18-20 0x00 0x01 0x12-0x14 Reserved
0 1 21 0x00 0x01 0x15 ASI2 DAC Format
0 1 22 0x00 0x01 0x16 ASI2 ADC Format
0 1 23 0x00 0x01 0x17 ASI2 Offset
0 1 24-26 0x00 0x01 0x18-0x1A Reserved
0 1 27 0x00 0x01 0x1B ASI2 ADC Path
0 1 28 0x00 0x01 0x1C ASI2 DAC BCLK
0 1 29 0x00 0x01 0x1D ASI2 DAC WCLK
0 1 30 0x00 0x01 0x1E ASI2 ADC BCLK
0 1 31 0x00 0x01 0x1F ASI2 ADC WCLK
0 1 32 0x00 0x01 0x20 ASI2 DIN/DOUT MUX
0 1 33 0x00 0x01 0x21 ASI2 BDIV Clock Select
0 1 34 0x00 0x01 0x22 ASI2 BDIV Clock Ratio
0 1 35 0x00 0x01 0x23 ASI2 WDIV Clock Ratio
0 1 36 0x00 0x01 0x24 ASI2 DAC Clock Output
0 1 37 0x00 0x01 0x25 ASI2 ADC Clock Output
0 1 38-60 0x00 0x01 0x26-0x3C Reserved
0 1 61 0x00 0x01 0x3D BCLK1_GPIO1 Pin
0 1 62 0x00 0x01 0x3E WCLK1_GPIO2 Pin
0 1 63 0x00 0x01 0x3F DOUT1_GPIO3 Pin
0 1 64 0x00 0x01 0x40 IRQ_GPIO4 Pin
0 1 65 0x00 0x01 0x41 BCLK2_GPIO5 Pin
0 1 66 0x00 0x01 0x42 WCLK2_GPIO6 Pinb
0 1 67 0x00 0x01 0x43 DOUT2_GPIO7 Pin
0 1 68 0x00 0x01 0x44 DIN2_GPIO8 Pin
0 1 69 0x00 0x01 0x45 ICC_CLK_GPIO9 Pin
0 1 70 0x00 0x01 0x46 ICC_GPIO10 Pin
0 1 71-76 0x00 0x01 0x47-0x4C Reserved
0 1 77 0x00 0x01 0x4D GPI Pin
0 1 78 0x00 0x01 0x4E Reserved
0 1 79 0x00 0x01 0x4F GPIO HIZ CTRL1
0 1 80 0x00 0x01 0x50 GPIO HIZ CTRL2
0 1 81 0x00 0x01 0x51 GPIO HIZ CTRL3
0 1 82 0x00 0x01 0x52 GPIO HIZ CTRL4
0 1 83 0x00 0x01 0x53 GPIO HIZ CTRL3
0 1 84-86 0x00 0x01 0x54-0x56 Reserved
0 1 87 0x00 0x01 0x57 GPIO Pin 1
0 1 88 0x00 0x01 0x58 GPIO Pin 2
0 1 89 0x00 0x01 0x59 GPIO Pin 3
0 1 90-107 0x00 0x01 0x5A-0x6B Reserved
0 1 108 0x00 0x01 0x6C Interrupt Control 1
0 1 109 0x00 0x01 0x6D Interrupt Control 2
0 1 110 0x00 0x01 0x6E Interrupt Control 3
0 1 111 0x00 0x01 0x6F Interrupt Control 4
0 1 112 0x00 0x01 0x70 Interrupt Control 5
0 1 113 0x00 0x01 0x71 Interrupt Control 6
0 1 114-127 0x00 0x01 0x72-0xFF Reserved Registers
0 2 0 0x00 0x01 0x00 Page Select Register
0 2 1-5 0x00 0x01 0x01-0x05 Reserved Registers
0 2 6 0x00 0x01 0x06 Ramp Generator Frequency
0 2 7-23 0x00 0x01 0x07x17 Reserved Registers
0 2 24 0x00 0x01 0x18 Inrush Optimization 1
0 2 25 0x00 0x01 0x19 Inrush Optimization 2
0 2 26 0x00 0x01 0x1A Inrush Optimization 3
0 2 27 0x00 0x01 0x1B Inrush Optimization 4
0 2 28-127 0x00 0x01 0x1C-0x7F Reserved Registers
100 0 0 0x64 0x00 0x00 Page Select Register
100 0 1 0x64 0x00 0x01 DAC Interpolation
100 0 2 0x64 0x00 0x02 ADC interpolation Register
100 0 3-6 0x64 0x00 0x03-0x06 Reserved Registers
100 0 7 0x64 0x00 0x07 DSP Mute Register
100 0 8-15 0x64 0x00 0x0F Reserved Registers
100 0 16 0x64 0x00 0x10 Interrupt 1 DSP
100 0 17 0x64 0x00 0x11 Interrupt 2 DSP
100 0 18 0x64 0x00 0x12 Condition 1 DSP
100 0 19 0x64 0x00 0x13 Condition 2 DSP
100 0 20 0x64 0x00 0x14 ISR and COND Control
100 0 21 0x64 0x00 0x15 DSP Control Register
100 0 22-26 0x64 0x00 0x16-0x1A Reserved Register
100 0 27 0x64 0x00 0x1B PLL CLKIN Divider
100 0 28 0x64 0x00 0x1C PLL J-VAL Divider
100 0 29 0x64 0x00 0x1D PLL D-VAL Divider 2
100 0 30 0x64 0x00 0x1E D-VAL Divider 1
100 0 31 0x64 0x00 0x1F DSP Clock
100 0 32 0x64 0x00 0x20 N-VAL Divider
100 0 33 0x64 0x00 0x21 MDAC-VAL Divider
100 0 34 0x64 0x00 0x22 MADC-VAL Divider
100 0 35-37 0x64 0x00 0x23-0x25 Reserved Register
100 0 38 0x64 0x00 0x26 Charge-pump Clock
100 0 39 0x64 0x00 0x27 Boost Clock
100 0 40 0x64 0x00 0x28 Ramp Clock 1
100 0 41-42 0x64 0x00 0x29-0x2A Reserved Register
100 0 43 0x64 0x00 0x2B Ramp Clock 2
100 0 44 0x64 0x00 0x2C Ramp Clock 3
100 0 45-126 0x64 0x00 0x2D-0x7E Reserved Register
100 0 127 0x64 0x00 0x7F Book Selection