SLASF39 December   2023 TAD5112-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
        4. 7.3.1.4 Phase-Locked Loop (PLL) and Clock Generation
        5. 7.3.1.5 Output Channel Configurations
        6. 7.3.1.6 Reference Voltage
        7. 7.3.1.7 Programmable Microphone Bias
        8. 7.3.1.8 Signal-Chain Processing
          1. 7.3.1.8.1 DAC Signal-Chain
            1. 7.3.1.8.1.1 Programmable Channel Gain and Digital Volume Control
            2. 7.3.1.8.1.2 Programmable Channel Gain Calibration
            3. 7.3.1.8.1.3 Programmable Digital High-Pass Filter
            4. 7.3.1.8.1.4 Programmable Digital Biquad Filters
            5. 7.3.1.8.1.5 Programmable Digital Mixer
            6. 7.3.1.8.1.6 Configurable Digital Interpolation Filters
              1. 7.3.1.8.1.6.1 Linear Phase Filters
                1. 7.3.1.8.1.6.1.1 Sampling Rate: 16 kHz or 14.7 kHz
                2. 7.3.1.8.1.6.1.2 Sampling Rate: 24 kHz or 22.05 kHz
                3. 7.3.1.8.1.6.1.3 Sampling Rate: 32 kHz or 29.4 kHz
                4. 7.3.1.8.1.6.1.4 Sampling Rate: 48 kHz or 44.1 kHz
                5. 7.3.1.8.1.6.1.5 Sampling Rate: 96 kHz or 88.2 kHz
                6. 7.3.1.8.1.6.1.6 Sampling Rate: 384 kHz or 352.8 kHz
        9. 7.3.1.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 TAD5212_P0 Registers
      2. 7.5.2 TAD5212_P1 Registers
      3. 7.5.3 TAD5212_P3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.3 TAD5212_P3 Registers

Table 7-158 lists the memory-mapped registers for the TAD5212_P3 registers. All register offset addresses not listed in Table 7-158 should be considered as reserved locations and the register contents should not be modified.

Table 7-158 TAD5212_P3 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00PAGE_CFG Register (Address = 0x0) [Reset = 0x00]
0x1ASASI_CFG0Secondary ASI configuration register 00x30SASI_CFG0 Register (Address = 0x1A) [Reset = 0x30]
0x1BSASI_TX_CFG0SASI TX configuration register 00x00SASI_TX_CFG0 Register (Address = 0x1B) [Reset = 0x00]
0x1CSASI_TX_CFG1SASI TX configuration register 10x00SASI_TX_CFG1 Register (Address = 0x1C) [Reset = 0x00]
0x1DSASI_TX_CFG2SASI TX configuration register 20x00SASI_TX_CFG2 Register (Address = 0x1D) [Reset = 0x00]
0x20SASI_TX_CH3_CFGSASI TX Channel 3 configuration register0x02SASI_TX_CH3_CFG Register (Address = 0x20) [Reset = 0x02]
0x21SASI_TX_CH4_CFGSASI TX Channel 4 configuration register0x03SASI_TX_CH4_CFG Register (Address = 0x21) [Reset = 0x03]
0x22SASI_TX_CH5_CFGSASI TX Channel 5 configuration register0x04SASI_TX_CH5_CFG Register (Address = 0x22) [Reset = 0x04]
0x23SASI_TX_CH6_CFGSASI TX Channel 6 configuration register0x05SASI_TX_CH6_CFG Register (Address = 0x23) [Reset = 0x05]
0x24SASI_TX_CH7_CFGSASI TX Channel 7 configuration register0x06SASI_TX_CH7_CFG Register (Address = 0x24) [Reset = 0x06]
0x25SASI_TX_CH8_CFGSASI TX Channel 8 configuration register0x07SASI_TX_CH8_CFG Register (Address = 0x25) [Reset = 0x07]
0x26SASI_RX_CFG0SASI RX configuration register 00x00SASI_RX_CFG0 Register (Address = 0x26) [Reset = 0x00]
0x27SASI_RX_CFG1SASI RX configuration register 10x00SASI_RX_CFG1 Register (Address = 0x27) [Reset = 0x00]
0x28SASI_RX_CH1_CFGSASI RX Channel 1 configuration register0x00SASI_RX_CH1_CFG Register (Address = 0x28) [Reset = 0x00]
0x29SASI_RX_CH2_CFGSASI RX Channel 2 configuration register0x01SASI_RX_CH2_CFG Register (Address = 0x29) [Reset = 0x01]
0x2ASASI_RX_CH3_CFGSASI RX Channel 3 configuration register0x02SASI_RX_CH3_CFG Register (Address = 0x2A) [Reset = 0x02]
0x2BSASI_RX_CH4_CFGSASI RX Channel 4 configuration register0x03SASI_RX_CH4_CFG Register (Address = 0x2B) [Reset = 0x03]
0x2CSASI_RX_CH5_CFGSASI RX Channel 5 configuration register0x04SASI_RX_CH5_CFG Register (Address = 0x2C) [Reset = 0x04]
0x2DSASI_RX_CH6_CFGSASI RX Channel 6 configuration register0x05SASI_RX_CH6_CFG Register (Address = 0x2D) [Reset = 0x05]
0x2ESASI_RX_CH7_CFGSASI RX Channel 7 configuration register0x06SASI_RX_CH7_CFG Register (Address = 0x2E) [Reset = 0x06]
0x2FSASI_RX_CH8_CFGSASI RX Channel 8 configuration register0x07SASI_RX_CH8_CFG Register (Address = 0x2F) [Reset = 0x07]
0x32CLK_CFG12Clock configuration register 120x00CLK_CFG12 Register (Address = 0x32) [Reset = 0x00]
0x33CLK_CFG130x00CLK_CFG13 Register (Address = 0x33) [Reset = 0x00]
0x34CLK_CFG14Clock configuration register 140x10CLK_CFG14 Register (Address = 0x34) [Reset = 0x10]
0x35CLK_CFG15Clock configuration register 150x01CLK_CFG15 Register (Address = 0x35) [Reset = 0x01]
0x36CLK_CFG16Clock configuration register 160x00CLK_CFG16 Register (Address = 0x36) [Reset = 0x00]
0x37CLK_CFG17Clock configuration register 170x00CLK_CFG17 Register (Address = 0x37) [Reset = 0x00]
0x38CLK_CFG18Clock configuration register 180x08CLK_CFG18 Register (Address = 0x38) [Reset = 0x08]
0x39CLK_CFG19Clock configuration register 190x20CLK_CFG19 Register (Address = 0x39) [Reset = 0x20]
0x3ACLK_CFG20Clock configuration register 200x04CLK_CFG20 Register (Address = 0x3A) [Reset = 0x04]
0x3BCLK_CFG21Clock configuration register 210x00CLK_CFG21 Register (Address = 0x3B) [Reset = 0x00]
0x3CCLK_CFG22Clock configuration register 180x01CLK_CFG22 Register (Address = 0x3C) [Reset = 0x01]
0x3DCLK_CFG23Clock configuration register 180x01CLK_CFG23 Register (Address = 0x3D) [Reset = 0x01]
0x3ECLK_CFG24Clock configuration register 210x01CLK_CFG24 Register (Address = 0x3E) [Reset = 0x01]
0x44CLK_CFG300x00CLK_CFG30 Register (Address = 0x44) [Reset = 0x00]
0x45CLK_CFG310x00CLK_CFG31 Register (Address = 0x45) [Reset = 0x00]
0x46CLKOUT_CFG1CLKOUT configuration register 10x00CLKOUT_CFG1 Register (Address = 0x46) [Reset = 0x00]
0x47CLKOUT_CFG2CLKOUT configuration register 20x01CLKOUT_CFG2 Register (Address = 0x47) [Reset = 0x01]
0x49SARCLK_CFG1SAR clock configuration register 10x00SARCLK_CFG1 Register (Address = 0x49) [Reset = 0x00]

7.5.3.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 7-159.

Return to the Summary Table.

The device memory map is divided into pages. This register sets the page.

Table 7-159 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

7.5.3.2 SASI_CFG0 Register (Address = 0x1A) [Reset = 0x30]

SASI_CFG0 is shown in Table 7-160.

Return to the Summary Table.

This register is the ASI configuration register 0.

Table 7-160 SASI_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6SASI_FORMAT[1:0]R/W00bSecondary ASI protocol format.
0d = TDM mode
1d = I2S mode
2d = LJ (left-justified) mode
3d = Reserved; Don't use
5-4SASI_WLEN[1:0]R/W11bSecondary ASI word or slot length.
0d = 16 bits (Recommended this setting to be used with 10-kΩ input impedance configuration)
1d = 20 bits
2d = 24 bits
3d = 32 bits
3SASI_FSYNC_POLR/W0bASI FSYNC polarity (for SASI protocol only).
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
2SASI_BCLK_POLR/W0bASI BCLK polarity (for SASI protocol only).
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
1SASI_BUS_ERRR/W0bASI bus error detection.
0d = Enable bus error detection
1d = Disable bus error detection
0SASI_BUS_ERR_RCOVR/W0bASI bus error auto resume.
0d = Enable auto resume after bus error recovery
1d = Disable auto resume after bus error recovery and remain powered down until host configures the device

7.5.3.3 SASI_TX_CFG0 Register (Address = 0x1B) [Reset = 0x00]

SASI_TX_CFG0 is shown in Table 7-161.

Return to the Summary Table.

This register is the SASI TX configuration register 0.

Table 7-161 SASI_TX_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7SASI_TX_EDGER/W0bSecondary ASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in SASI_BCLK_POL
1d = Inverted following edge (half cycle delay) with respect to the default edge setting
6SASI_TX_FILLR/W0bSecondary ASI data output (on the primary and secondary data pin) for any unused cycles
0d = Always transmit 0 for unused cycles
1d = Always use Hi-Z for unused cycles
5SASI_TX_LSBR/W0bSecondary ASI data output (on the primary and secondary data pin) for LSB transmissions.
0d = Transmit the LSB for a full cycle
1d = Transmit the LSB for the first half cycle and Hi-Z for the second half cycle
4-3SASI_TX_KEEPER[1:0]R/W00bSecondary ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled
1d = Bus keeper is always enabled
2d = Bus keeper is enabled during LSB transmissions only for one cycle
3d = Bus keeper is enabled during LSB transmissions only for one and half cycles
2SASI_TX_USE_INT_FSYNCR/W0bSecondary ASI uses internal FSYNC for output data generation in controller mode configuration as applicable.
0d = Use external FSYNC for ASI protocol data generation
1d = Use internal FSYNC for ASI protocol data generation
1SASI_TX_USE_INT_BCLKR/W0bSecondary ASI uses internal BCLK for output data generation in controller mode configuration.
0d = Use external BCLK for ASI protocol data generation
1d = Use internal BCLK for ASI protocol data generation
0SASI_TDM_PULSE_WIDTHR/W0bSecondary ASI fsync pulse width in TDM format.
0d = Fsync pulse is 1 bclk period wide
1d = Fsync pulse is 2 bclk period wide

7.5.3.4 SASI_TX_CFG1 Register (Address = 0x1C) [Reset = 0x00]

SASI_TX_CFG1 is shown in Table 7-162.

Return to the Summary Table.

This register is the SASI TX configuration register 1.

Table 7-162 SASI_TX_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR000bReserved bits; Write only reset value
4-0SASI_TX_OFFSET[4:0]R/W00000bSecondary ASI output data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

7.5.3.5 SASI_TX_CFG2 Register (Address = 0x1D) [Reset = 0x00]

SASI_TX_CFG2 is shown in Table 7-163.

Return to the Summary Table.

This register is the SASI TX configuration register 2.

Table 7-163 SASI_TX_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7SASI_TX_CH8_SELR/W0bSecondary ASI output channel 8 select.
0d = Secondary ASI channel 8 output is on DOUT
1d = Secondary ASI channel 8 output is on DOUT2
6SASI_TX_CH7_SELR/W0bSecondary ASI output channel 7 select.
0d = Secondary ASI channel 7 output is on DOUT
1d = Secondary ASI channel 7 output is on DOUT2
5SASI_TX_CH6_SELR/W0bSecondary ASI output channel 6 select.
0d = Secondary ASI channel 6 output is on DOUT
1d = Secondary ASI channel 6 output is on DOUT2
4SASI_TX_CH5_SELR/W0bSecondary ASI output channel 5 select.
0d = Secondary ASI channel 5 output is on DOUT
1d = Secondary ASI channel 5 output is on DOUT2
3SASI_TX_CH4_SELR/W0bSecondary ASI output channel 4 select.
0d = Secondary ASI channel 4 output is on DOUT
1d = Secondary ASI channel 4 output is on DOUT2
2SASI_TX_CH3_SELR/W0bSecondary ASI output channel 3 select.
0d = Secondary ASI channel 3 output is on DOUT
1d = Secondary ASI channel 3 output is on DOUT2
1RESERVEDR/W0bReserved bit; Write only reset value
0RESERVEDR/W0bReserved bit; Write only reset value

7.5.3.6 SASI_TX_CH3_CFG Register (Address = 0x20) [Reset = 0x02]

SASI_TX_CH3_CFG is shown in Table 7-164.

Return to the Summary Table.

This register is the SASI TX Channel 3 configuration register.

Table 7-164 SASI_TX_CH3_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_TX_CH3_CFG[1:0]R/W00bSecondary ASI output channel 3 configuration.
0d = Secondary ASI channel 3 output is in a tri-state condition
Dont use
2d = Secondary ASI channel 3 output corresponds to VBAT data
3d = Reserved
4-0SASI_TX_CH3_SLOT_NUM[4:0]R/W00010bSecondary ASI output channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.7 SASI_TX_CH4_CFG Register (Address = 0x21) [Reset = 0x03]

SASI_TX_CH4_CFG is shown in Table 7-165.

Return to the Summary Table.

This register is the SASI TX Channel 4 configuration register.

Table 7-165 SASI_TX_CH4_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_TX_CH4_CFG[1:0]R/W00bSecondary ASI output channel 4 configuration.
0d = Secondary ASI channel 4 output is in a tri-state condition
Dont use
2d = Secondary ASI channel 4 output corresponds to TEMP data
3d = Reserved
4-0SASI_TX_CH4_SLOT_NUM[4:0]R/W00011bSecondary ASI output channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.8 SASI_TX_CH5_CFG Register (Address = 0x22) [Reset = 0x04]

SASI_TX_CH5_CFG is shown in Table 7-166.

Return to the Summary Table.

This register is the SASI TX Channel 5 configuration register.

Table 7-166 SASI_TX_CH5_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_TX_CH5_CFG[1:0]R/W00bSecondary ASI output channel 5 configuration.
0d = Secondary ASI channel 5 output is in a tri-state condition
1d = Secondary ASI channel 5 output corresponds to ASI Input Channel 1 loopback data
2d = Secondary ASI channel 5 output corresponds to echo reference channel 1 data
3d = Reserved
4-0SASI_TX_CH5_SLOT_NUM[4:0]R/W00100bSecondary ASI output channel 5 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.9 SASI_TX_CH6_CFG Register (Address = 0x23) [Reset = 0x05]

SASI_TX_CH6_CFG is shown in Table 7-167.

Return to the Summary Table.

This register is the SASI TX Channel 6 configuration register.

Table 7-167 SASI_TX_CH6_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_TX_CH6_CFG[1:0]R/W00bSecondary ASI output channel 6 configuration.
0d = Secondary ASI channel 6 output is in a tri-state condition
1d = Secondary ASI channel 6 output corresponds to ASI Input Channel 2 loopback data
2d = Secondary ASI channel 6 output corresponds to echo reference channel 2 data
3d = Reserved
4-0SASI_TX_CH6_SLOT_NUM[4:0]R/W00101bSecondary ASI output channel 6 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.10 SASI_TX_CH7_CFG Register (Address = 0x24) [Reset = 0x06]

SASI_TX_CH7_CFG is shown in Table 7-168.

Return to the Summary Table.

This register is the SASI TX Channel 7 configuration register.

Table 7-168 SASI_TX_CH7_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_TX_CH7_CFG[1:0]R/W00bSecondary ASI output channel 7 configuration.
0d = Secondary ASI channel 7 output is in a tri-state condition
1d = Secondary ASI channel 7 output corresponds to {VBAT_WLby2, TEMP_WLby2}
2d = Secondary ASI channel 7 output corresponds to {echo_ref_ch1_wlby2, echo_ref_ch2_wlby2}
3d = Reserved
4-0SASI_TX_CH7_SLOT_NUM[4:0]R/W00110bSecondary ASI output channel 7 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.11 SASI_TX_CH8_CFG Register (Address = 0x25) [Reset = 0x07]

SASI_TX_CH8_CFG is shown in Table 7-169.

Return to the Summary Table.

This register is the SASI TX Channel 8 configuration register.

Table 7-169 SASI_TX_CH8_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5SASI_TX_CH8_CFGR/W0bSecondary ASI output channel 8 configuration.
0d = Secondary ASI channel 8 output is in a tri-state condition
1d = Secondary ASI channel 8 output corresponds to ICLA data
4-0SASI_TX_CH8_SLOT_NUM[4:0]R/W00111bSecondary ASI output channel 8 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.12 SASI_RX_CFG0 Register (Address = 0x26) [Reset = 0x00]

SASI_RX_CFG0 is shown in Table 7-170.

Return to the Summary Table.

This register is the SASI RX configuration register 0.

Table 7-170 SASI_RX_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7SASI_RX_EDGER/W0bSecondary ASI data input (on the primary and secondary data pin) receive edge.
0d = Default edge as per the protocol configuration setting in bit 2 (BCLK_POL)
1d = Inverted following edge (half cycle delay) with respect to the default edge setting
6SASI_RX_USE_INT_FSYNCR/W0bSecondary ASI uses internal FSYNC for input data latching in controller mode configuration as applicable.
0d = Use external FSYNC for ASI protocol data latching
1d = Use internal FSYNC for ASI protocol data latching
5SASI_RX_USE_INT_BCLKR/W0bSecondary ASI uses internal BCLK for input data latching in controller mode configuration.
0d = Use external BCLK for ASI protocol data latching
1d = Use internal BCLK for ASI protocol data latching
4-0SASI_RX_OFFSET[4:0]R/W00000bSecondary ASI data input MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

7.5.3.13 SASI_RX_CFG1 Register (Address = 0x27) [Reset = 0x00]

SASI_RX_CFG1 is shown in Table 7-171.

Return to the Summary Table.

This register is the SASI RX configuration register 1.

Table 7-171 SASI_RX_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7SASI_RX_CH8_SELR/W0bSecondary ASI input channel 8 select.
0d = Secondary ASI channel 8 input is on DIN
1d = Secondary ASI channel 8 input is on DIN2
6SASI_RX_CH7_SELR/W0bSecondary ASI input channel 7 select.
0d = Secondary ASI channel 7 input is on DIN
1d = Secondary ASI channel 7 input is on DIN2
5SASI_RX_CH6_SELR/W0bSecondary ASI input channel 6 select.
0d = Secondary ASI channel 6 input is on DIN
1d = Secondary ASI channel 6 input is on DIN2
4SASI_RX_CH5_SELR/W0bSecondary ASI input channel 5 select.
0d = Secondary ASI channel 5 input is on DIN
1d = Secondary ASI channel 5 input is on DIN2
3SASI_RX_CH4_SELR/W0bSecondary ASI input channel 4 select.
0d = Secondary ASI channel 4 input is on DIN
1d = Secondary ASI channel 4 input is on DIN2
2SASI_RX_CH3_SELR/W0bSecondary ASI input channel 3 select.
0d = Secondary ASI channel 3 input is on DIN
1d = Secondary ASI channel 3 input is on DIN2
1SASI_RX_CH2_SELR/W0bSecondary ASI input channel 2 select.
0d = Secondary ASI channel 2 input is on DIN
1d = Secondary ASI channel 2 input is on DIN2
0SASI_RX_CH1_SELR/W0bSecondary ASI input channel 1 select.
0d = Secondary ASI channel 1 input is on DIN
1d = Secondary ASI channel 1 input is on DIN2

7.5.3.14 SASI_RX_CH1_CFG Register (Address = 0x28) [Reset = 0x00]

SASI_RX_CH1_CFG is shown in Table 7-172.

Return to the Summary Table.

This register is the SASI RX Channel 1 configuration register.

Table 7-172 SASI_RX_CH1_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5SASI_RX_CH1_CFGR/W0bSecondary ASI input channel 1 configuration.
0d = Secondary ASI channel 1 input is disabled
1d = Secondary ASI channel 1 input corresponds to DAC Channel 1 data
4-0SASI_RX_CH1_SLOT_NUM[4:0]R/W00000bSecondary ASI input channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.15 SASI_RX_CH2_CFG Register (Address = 0x29) [Reset = 0x01]

SASI_RX_CH2_CFG is shown in Table 7-173.

Return to the Summary Table.

This register is the SASI RX Channel 2 configuration register.

Table 7-173 SASI_RX_CH2_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5SASI_RX_CH2_CFGR/W0bSecondary ASI input channel 2 configuration.
0d = Secondary ASI channel 2 input is disabled
1d = Secondary ASI channel 2 input corresponds to DAC Channel 2 data
4-0SASI_RX_CH2_SLOT_NUM[4:0]R/W00001bSecondary ASI input channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.16 SASI_RX_CH3_CFG Register (Address = 0x2A) [Reset = 0x02]

SASI_RX_CH3_CFG is shown in Table 7-174.

Return to the Summary Table.

This register is the SASI RX Channel 3 configuration register.

Table 7-174 SASI_RX_CH3_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5SASI_RX_CH3_CFGR/W0bSecondary ASI input channel 3 configuration.
0d = Secondary ASI channel 3 input is disabled
1d = Secondary ASI channel 3 input corresponds to DAC Channel 3 data
4-0SASI_RX_CH3_SLOT_NUM[4:0]R/W00010bSecondary ASI input channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.17 SASI_RX_CH4_CFG Register (Address = 0x2B) [Reset = 0x03]

SASI_RX_CH4_CFG is shown in Table 7-175.

Return to the Summary Table.

This register is the SASI RX Channel 4 configuration register.

Table 7-175 SASI_RX_CH4_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5SASI_RX_CH4_CFGR/W0bSecondary ASI input channel 4 configuration.
0d = Secondary ASI channel 4 input is disabled
1d = Secondary ASI channel 4 input corresponds to DAC Channel 4 data
4-0SASI_RX_CH4_SLOT_NUM[4:0]R/W00011bSecondary ASI input channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.18 SASI_RX_CH5_CFG Register (Address = 0x2C) [Reset = 0x04]

SASI_RX_CH5_CFG is shown in Table 7-176.

Return to the Summary Table.

This register is the SASI RX Channel 5 configuration register.

Table 7-176 SASI_RX_CH5_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_RX_CH5_CFG[1:0]R/W00bSecondary ASI input channel 5 configuration.
0d = Secondary ASI channel 5 input is disabled
1d = Secondary ASI channel 5 input corresponds to DAC Channel 5 data
2d = Secondary ASI channel 5 input corresponds to ADC Channel 1 output loopback
3d = Reserved
4-0SASI_RX_CH5_SLOT_NUM[4:0]R/W00100bSecondary ASI input channel 5 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.19 SASI_RX_CH6_CFG Register (Address = 0x2D) [Reset = 0x05]

SASI_RX_CH6_CFG is shown in Table 7-177.

Return to the Summary Table.

This register is the SASI RX Channel 6 configuration register.

Table 7-177 SASI_RX_CH6_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_RX_CH6_CFG[1:0]R/W00bSecondary ASI input channel 6 configuration.
0d = Secondary ASI channel 6 input is disabled
1d = Secondary ASI channel 6 input corresponds to DAC Channel 6 data
2d = Secondary ASI channel 6 input corresponds to ADC Channel 2 output loopback
3d = Secondary ASI channel 6 input corresponds to ICLA device 1 data
4-0SASI_RX_CH6_SLOT_NUM[4:0]R/W00101bSecondary ASI input channel 6 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.20 SASI_RX_CH7_CFG Register (Address = 0x2E) [Reset = 0x06]

SASI_RX_CH7_CFG is shown in Table 7-178.

Return to the Summary Table.

This register is the SASI RX Channel 7 configuration register.

Table 7-178 SASI_RX_CH7_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_RX_CH7_CFG[1:0]R/W00bSecondary ASI input channel 7 configuration.
0d = Secondary ASI channel 7 input is disabled
1d = Secondary ASI channel 7 input corresponds to DAC Channel 7 data
2d = Secondary ASI channel 7 input corresponds to ADC Channel 3 output loopback
3d = Secondary ASI channel 7 input corresponds to ICLA device 2 data
4-0SASI_RX_CH7_SLOT_NUM[4:0]R/W00110bSecondary ASI input channel 7 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.21 SASI_RX_CH8_CFG Register (Address = 0x2F) [Reset = 0x07]

SASI_RX_CH8_CFG is shown in Table 7-179.

Return to the Summary Table.

This register is the SASI RX Channel 8 configuration register.

Table 7-179 SASI_RX_CH8_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5SASI_RX_CH8_CFG[1:0]R/W00bSecondary ASI input channel 8 configuration.
0d = Secondary ASI channel 8 input is disabled
1d = Secondary ASI channel 8 input corresponds to DAC Channel 8 data
2d = Secondary ASI channel 8 input corresponds to ADC Channel 4 output loopback
3d = Secondary ASI channel 8 input corresponds to ICLA device 3 data
4-0SASI_RX_CH8_SLOT_NUM[4:0]R/W00111bSecondary ASI input channel 8 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.5.3.22 CLK_CFG12 Register (Address = 0x32) [Reset = 0x00]

CLK_CFG12 is shown in Table 7-180.

Return to the Summary Table.

This register is the clock configuration register 12.

Table 7-180 CLK_CFG12 Register Field Descriptions
BitFieldTypeResetDescription
7-6PDIV_CLKSRC_SEL[1:0]R/W00bSource clock selection for PLL PDIV Divider.
0d = PLL_PDIV_IN_CLK is Primary ASI BCLK
1d = PLL_PDIV_IN_CLK is Secondary ASI BCLK
2d = PLL_PDIV_IN_CLK is CCLK
3d = PLL_PDIV_IN_CLK is internal Oscillator Clock
5-3PASI_BCLK_DIV_CLK_SEL[2:0]R/W000bPrimary ASI BCLK divider clock source selection.
0d = Primary ASI BCLK divider clock source is PLL output
1d = Reserved
2d = Primary ASI BCLK divider clock source is secondary ASI BCLK
3d = Primary ASI BCLK divider clock source is CCLK
4d = Primary ASI BCLK divider clock source is internal oscillator clock
5d = Primary ASI BCLK divider clock source is DSP clock
6d to 7d = Reserved
2-0RESERVEDR000bReserved bits; Write only reset value

7.5.3.23 CLK_CFG13 Register (Address = 0x33) [Reset = 0x00]

CLK_CFG13 is shown in Table 7-181.

Return to the Summary Table.

Table 7-181 CLK_CFG13 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-4SASI_BCLK_DIV_CLK_SEL[2:0]R/W000bSecondaary ASI BCLK divider clock source selection.
0d = Secondaary ASI BCLK divider clock source is PLL output
1d = Secondaary ASI BCLK divider clock source is primary ASI BCLK
2d = Reserved
3d = Secondaary ASI BCLK divider clock source is CCLK
4d = Secondaary ASI BCLK divider clock source is internal oscillator clock
5d = Secondaary ASI BCLK divider clock source is DSP clock
6d to 7d = Reserved
3-0RESERVEDR0000bReserved bits; Write only reset value

7.5.3.24 CLK_CFG14 Register (Address = 0x34) [Reset = 0x10]

CLK_CFG14 is shown in Table 7-182.

Return to the Summary Table.

This register is the clock configuration register 14.

Table 7-182 CLK_CFG14 Register Field Descriptions
BitFieldTypeResetDescription
7-6DIG_NM_DIV_CLK_SRC_SEL[1:0]R/W00bSource clock selection for DIG NMDIV CLK clock.
0d = DIG NM divider input clock is Primary ASI BCLK
1d = DIG NM divider input clock is Secondary ASI BCLK
2d = DIG NM divider input clock is CCLK
3d = DIG NM divider input clock is internal oscillator clock
5-4ANA_NM_DIV_CLK_SRC_SEL[1:0]R/W01bSource clock selection for NMDIV CLK clock.
0d = NM divider input clock is PLL Output
1d = NM divider input clock is PLL Output
2d = NM divider input clock is DIG NM Divider Clock Source
3d = NM divider input clock is Primary ASI BCLK (Low Jitter Path)
3-2RESERVEDR/W00bReserved bits; Write only reset values
1-0RESERVEDR/W00bReserved bits; Write only reset values

7.5.3.25 CLK_CFG15 Register (Address = 0x35) [Reset = 0x01]

CLK_CFG15 is shown in Table 7-183.

Return to the Summary Table.

This register is the clock configuration register 15.

Table 7-183 CLK_CFG15 Register Field Descriptions
BitFieldTypeResetDescription
7-0PLL_PDIV[7:0]R/W00000001bPLL pre-scaler P-divider value (Don't care when auto detection is enabled)
0d = PLL PDIV value is 256
1d = PLL PDIV value is 1
2d = PLL PDIV value is 2
3d to 254d = PLL PDIV value is as per configuration
255d = PLL PDIV value is 255

7.5.3.26 CLK_CFG16 Register (Address = 0x36) [Reset = 0x00]

CLK_CFG16 is shown in Table 7-184.

Return to the Summary Table.

This register is the clock configuration register 16.

Table 7-184 CLK_CFG16 Register Field Descriptions
BitFieldTypeResetDescription
7PLL_JMUL_MSBR/W0bPLL integer portion J-multiplier value MSB bit. (Don't care when auto detection is enabled)
6PLL_DIV_CLK_DIG_BY_2R/W0bPLL DIV clock divide by 2 configuration
0d = No divide/2 inside PLL
1d = PLL does a divide/2
5-0PLL_DMUL_MSB[5:0]R/W000000bPLL fractional portion D-multiplier value MSB bits. (Don't care when auto detection is enabled)

7.5.3.27 CLK_CFG17 Register (Address = 0x37) [Reset = 0x00]

CLK_CFG17 is shown in Table 7-185.

Return to the Summary Table.

This register is the clock configuration register 17.

Table 7-185 CLK_CFG17 Register Field Descriptions
BitFieldTypeResetDescription
7-0PLL_DMUL_LSB[7:0]R/W00000000bPLL fractional portion D-multiplier value LSB byte. Above D-multiplier value MSB bits (PLL_DMUL_MSB) along with this LSB byte (PLL_DMUL_LSB) is concatenated to determine final D-multiplier value. (Don't care when auto detection is enabled)
0d = PLL DMUL value is 0
1d = PLL DMUL value is 1
2d = PLL DMUL value is 2
3d to 9998d = PLL JMUL value is as per configuration
9999d = PLL JMUL value is 9999
10000d to 16383d = Reserved; Don't use

7.5.3.28 CLK_CFG18 Register (Address = 0x38) [Reset = 0x08]

CLK_CFG18 is shown in Table 7-186.

Return to the Summary Table.

This register is the clock configuration register 18.

Table 7-186 CLK_CFG18 Register Field Descriptions
BitFieldTypeResetDescription
7-0PLL_JMUL_LSB[7:0]R/W00001000bPLL integer portion J-multiplier value LSB byte. Above J-multiplier value MSB bit (PLL_JMUL_MSB) along with this LSB byte (PLL_JMUL_LSB) is concatenated to determine fianl J-multiplier value. (Don't care when auto detection is enabled)
0d = Reserved; Don't use
1d = PLL JMUL value is 1
2d = PLL JMUL value is 2
3d to 510d = PLL JMUL value is as per configuration
511d = PLL JMUL value is 511

7.5.3.29 CLK_CFG19 Register (Address = 0x39) [Reset = 0x20]

CLK_CFG19 is shown in Table 7-187.

Return to the Summary Table.

This register is the clock configuration register 19.

Table 7-187 CLK_CFG19 Register Field Descriptions
BitFieldTypeResetDescription
7-5NDIV[2:0]R/W001bNDIV divider value. (Don't care when auto detection is enabled)
0d = NDIV value is 8
1d = NDIV value is 1
2d = NDIV value is 2
3d to 6d = NDIV value is as per configuration
7d = NDIV value is 7
4-2PDM_DIV[2:0]R/W000bPDM divider value. (Don't care when auto detection is enabled)
0d = PDM_DIV value is 1
1d = PDM_DIV value is 2
2d = PDM_DIV value is 4
3d = PDM_DIV value is 8
4d = PDM_DIV value is 16
5d-7d Reserved
1-0RESERVEDR/W00bReserved bits; Write only reset values

7.5.3.30 CLK_CFG20 Register (Address = 0x3A) [Reset = 0x04]

CLK_CFG20 is shown in Table 7-188.

Return to the Summary Table.

This register is the clock configuration register 20.

Table 7-188 CLK_CFG20 Register Field Descriptions
BitFieldTypeResetDescription
7-2MDIV[5:0]R/W000001bMDIV divider value. (Don't care when auto detection is enabled)
0d = MDIV value is 64
1d = MDIV value is 1
2d = MDIV value is 2
3d to 62d = MDIV value is as per configuration
63d = MDIV value is 63
1-0RESERVEDR/W00bReserved bits; Write only reset values

7.5.3.31 CLK_CFG21 Register (Address = 0x3B) [Reset = 0x00]

CLK_CFG21 is shown in Table 7-189.

Return to the Summary Table.

This register is the clock configuration register 21.

Table 7-189 CLK_CFG21 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00bReserved bits; Write only reset values
5-4DIG_DAC_MODCLK_DIV[1:0]R/W00bDAC modulator clock divider value. (Don't care when auto detection is enabled)
0d = DIG_DAC_MODCLK_DIV value is 1
1d = DIG_DAC_MODCLK_DIV value is 2
2d = DIG_DAC_MODCLK_DIV value is 4
3d = Reserved
3RESERVEDR/W0bReserved bit; Write only reset value
2PASI_BDIV_MSBR/W0bPrimary ASI BCLK divider value MSB bit. (Don't care when auto detection is enabled)
1SASI_BDIV_MSBR/W0bSecondary ASI BCLK divider value MSB bit. (Don't care when auto detection is enabled)
0RESERVEDR0bReserved bit; Write only reset value

7.5.3.32 CLK_CFG22 Register (Address = 0x3C) [Reset = 0x01]

CLK_CFG22 is shown in Table 7-190.

Return to the Summary Table.

This register is the clock configuration register 18.

Table 7-190 CLK_CFG22 Register Field Descriptions
BitFieldTypeResetDescription
7-0PASI_BDIV_LSB[7:0]R/W00000001bSecondary ASI BCLK divider value. (Don't care when auto detection is enabled)
0d = SASI BCLK divider value is 512
1d = SASI BCLK divider value is 1
2d = SASI BCLK divider value is 2
3d to 62d = SASI BCLK divider value is as per configuration
63d = SASI BCLK divider value is 511

7.5.3.33 CLK_CFG23 Register (Address = 0x3D) [Reset = 0x01]

CLK_CFG23 is shown in Table 7-191.

Return to the Summary Table.

This register is the clock configuration register 18.

Table 7-191 CLK_CFG23 Register Field Descriptions
BitFieldTypeResetDescription
7-0SASI_BDIV_LSB[7:0]R/W00000001bSecondary ASI BCLK divider value. (Don't care when auto detection is enabled)
0d = SASI BCLK divider value is 512
1d = SASI BCLK divider value is 1
2d = SASI BCLK divider value is 2
3d to 62d = SASI BCLK divider value is as per configuration
63d = SASI BCLK divider value is 511

7.5.3.34 CLK_CFG24 Register (Address = 0x3E) [Reset = 0x01]

CLK_CFG24 is shown in Table 7-192.

Return to the Summary Table.

This register is the clock configuration register 21.

Table 7-192 CLK_CFG24 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset value
5-0ANA_NM_DIV[5:0]R/W000001bAnalog N-M DIV divider value. (Don't care when auto detection is enabled)
0d = ANA_NM_DIV value is 64
1d = ANA_NM_DIV value is 1
2d = ANA_NM_DIV value is 2
3d to 62d = ANA_NM_DIV value is as per configuration
63d = NDIV value is 63

7.5.3.35 CLK_CFG30 Register (Address = 0x44) [Reset = 0x00]

CLK_CFG30 is shown in Table 7-193.

Return to the Summary Table.

Table 7-193 CLK_CFG30 Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR00000bReserved bits; Write only reset value
2NDIV_ENR/W0bNDIV divider enable
0d = divider disabled
1d = divider enabled
1MDIV_ENR/W0bMDIV divider enable
0d = divider disabled
1d = divider enabled
0PDM_DIV_ENR/W0bPDM divider enable
0d = divider disabled
1d = divider enabled

7.5.3.36 CLK_CFG31 Register (Address = 0x45) [Reset = 0x00]

CLK_CFG31 is shown in Table 7-194.

Return to the Summary Table.

Table 7-194 CLK_CFG31 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6RESERVEDR/W0bReserved bit; Write only reset value
5RESERVEDR/W0bReserved bit; Write only reset value
4DIG_DAC_MODCLK_DIV_ENR/W0bDAC MODCLK divider enable
0d = divider disabled
1d = divider enabled
3PASI_BDIV_ENR/W0bPASI BDIV divider enable
0d = divider disabled
1d = divider enabled
2SASI_BDIV_ENR/W0bSASI BDIV divider enable
0d = divider disabled
1d = divider enabled
1PASI_FSYNC_DIV_ENR/W0bPASI FSYNC DIV divider enable
0d = divider disabled
1d = divider enabled
0SASI_FSYNC_DIV_ENR/W0bSASI FSYNC DIV divider enable
0d = divider disabled
1d = divider enabled

7.5.3.37 CLKOUT_CFG1 Register (Address = 0x46) [Reset = 0x00]

CLKOUT_CFG1 is shown in Table 7-195.

Return to the Summary Table.

This register is the CLKOUT configuration register 1.

Table 7-195 CLKOUT_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR00000bReserved bits; Write only reset value
2-0CLKOUT_CLK_SEL[2:0]R/W000bGeneral Purpose CLKOUT divider clock source selection.
0d = Source clock is PLL output
1d = Source clock is primary ASI BCLK
2d = Source clock is secondary ASI BCLK
3d = Source clock is CCLK
4d = Source clock is internal oscillator clock
5d = Source clock is DSP clock
6d to 7d = Reserved

7.5.3.38 CLKOUT_CFG2 Register (Address = 0x47) [Reset = 0x01]

CLKOUT_CFG2 is shown in Table 7-196.

Return to the Summary Table.

This register is the CLKOUT configuration register 2.

Table 7-196 CLKOUT_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7CLKOUT_DIV_ENR/W0bCLKOUT divider enable.
0d = CLKOUT divider disabled
1d = CLKOUT divider enabled
6-0CLKOUT_DIV[6:0]R/W0000001bCLKOUT DIV divider value.
0d = CLKOUT_DIV value is 128
1d = CLKOUT_DIV value is 1
2d = CLKOUT_DIV value is 2
3d to 126d = CLKOUT_DIV value is as per configuration
127d = CLKOUT_DIV value is 127

7.5.3.39 SARCLK_CFG1 Register (Address = 0x49) [Reset = 0x00]

SARCLK_CFG1 is shown in Table 7-197.

Return to the Summary Table.

This register is the SAR clock configuration register 1

Table 7-197 SARCLK_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6SAR_CLK_FREQ_SEL[1:0]R/W00bSAR clock frequency mode
0d = SAR clock frequency is ~6MHz
1d = SAR clock frequency is ~3MHz
2d = SAR clock frequency is ~1.5MHz
3d = SAR clock frequency is ~12MHz (valid only when SAR clock is generated directly using internal oscilator clock
5SAR_CLK_SRC_AUTO_DISR/W0bSAR divider source clock auto selection disable
0d = SAR divider source clock auto-selection based on clock detection scheme
1d = SAR divider source clock auto-selection disabled and selected based on BST_CLK_SRC_SEL
4SAR_CLK_SRC_MANUAL_SELR/W0bSAR clock source manual selection (don't care in auto mode)
0d = SAR clock generated based on Audio clock available for ADC/DAC
1d = SAR clock generated based on internal oscillator clock
3SAR_CLK_EN_AUTO_DISR/W0bSAR divider source clock auto selection disable
0d = SAR divider auto-enabled
1d = SAR divider enabled/disabled based on manual control using BST_CLK_EN
2SAR_CLK_MANUAL_ENR/W0bSAR divider manual enable (don't care in auto mode)
0d = SAR divider disabled
1d = SAR divider enabled
1-0SAR_CLK_MANUAL_DIV[1:0]R/W00bSAR divider value (don't care in auto mode)
0d = SAR divider value is 1
1d = SAR divider value is 2
2d = SAR divider value is 4
3d = SAR divider value is 8