请参考 PDF 数据表获取器件具体的封装图。
SN65176B 和 SN75176B 差分总线收发器旨在实现多点总线传输线路上的双向数据通信。这些器件专为平衡传输线路而设计,符合 ANSI 标准 TIA/EIA-422-B 和 TIA/EIA-485-A 以及 ITU 建议 V.11 和 X.27。
SN65176B 和 SN75176B 器件整合了一个三态差分线路驱动器和一个差分输入线路接收器,两者均采用 5V 单电源供电。驱动器和接收器分别具有高电平有效和低电平有效使能端,它们可以在外部连接在一起以用作方向控制。驱动器差分输出端和接收器差分输入端在内部连接以形成差分输入/输出 (I/O) 总线端口,这些端口用于在禁用驱动器或 VCC = 0 时为总线提供最小负载。这些端口具有较宽的正负共模电压范围,使得该器件适用于合用线应用。
驱动器旨在实现高达 60mA 的灌电流或拉电流。驱动器具有正负电流限制和热关断功能,避免出现线路故障状况。根据设计在大约 150°C 的结温下发生热关断。接收器具有 12kΩ 的最小输入阻抗、±200mV 的输入灵敏度和 50mV 的典型输入迟滞。
器件型号 | 封装(引脚)(1) | 封装尺寸(标称值) |
---|---|---|
SNx5176 | SOIC (8) | 4.90mm × 3.91mm |
PDIP (8) | 9.81mm × 6.35mm | |
SOP (8) | 6.20mm × 5.30mm |
Changes from Revision G (July 2021) to Revision H (December 2021)
Changes from Revision F (January 2015) to Revision G (July 2021)
Changes from Revision E (January 2014) to Revision F (January 2015)
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
R | 1 | O | Logic Data Output from RS-485 Receiver |
RE | 2 | I | Receive Enable (active low) |
DE | 3 | I | Driver Enable (active high) |
D | 4 | I | Logic Data Input to RS-485 Driver |
GND | 5 | — | Device Ground Pin |
A | 6 | I/O | RS-422 or RS-485 Data Line |
B | 7 | I/O | RS-422 or RS-485 Data Line |
VCC | 8 | — | Power Input. Connect to 5-V Power Source. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage(2) | 7 | V | ||
Voltage range at any bus terminal | –10 | 15 | V | ||
VI | Enable input voltage | 5.5 | V | ||
TJ | Operating virtual junction temperature | 150 | °C | ||
Tstg | Storage temperature range | –65 | 150 | °C | |
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds | 260 | °C |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | 4.75 | 5 | 5.25 | V | |
VI or VIC | Voltage at any bus terminal (separately or common mode) | -7 | 12 | V | ||
VIH | High-level input voltage | D, DE, and RE | 2 | V | ||
VIL | Low-level input voltage | D, DE, and RE | 0.8 | V | ||
VID | Differential input voltage(1) | ±12 | V | |||
IOH | High-level output current | Driver | –60 | mA | ||
Receiver | –400 | µA | ||||
IOL | Low-level output current | Driver | 60 | mA | ||
Receiver | 8 | |||||
TA | Operating free-air temperature | SN65176B | –40 | 105 | °C | |
SN75176B | 0 | 70 |
THERMAL METRIC(1) | SNx5176 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | PS (SO) | P (PDIP) | |||
8 PINS | |||||
RθJA | Junction-to-ambient thermal resistance | 114.4 | 113.2 | 88.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 55.1 | 57.9 | 65.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 61.6 | 69.0 | 69.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 8.8 | 14.6 | 35.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 60.8 | 68.1 | 64.3 | °C/W |
PARAMETER | TEST CONDITIONS(1) | MIN | TYP(2) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIK | Input clamp voltage | II = –18 mA | –1.5 | V | |||
VO | Output voltage | IO = 0 | 0 | Vcc | V | ||
|VOD1| | Differential output voltage | IO = 0 | 1.5 | 3.6 | Vcc | V | |
|VOD2| | Differential output voltage | RL = 100 Ω, see Figure 7-1 | ½ VOD1 or 2 (4) | V | |||
RL = 54 Ω, see Figure 7-1 | 1.5 | 2.5 | 5 | ||||
VOD3 | Differential output voltage | See (5) | 1.5 | 5 | V | ||
∆|VOD| | Change in magnitude of differential output voltage(3) | RL = 54 Ω or 100 Ω, see Figure 7-1 | ±0.2 | V | |||
VOC | Common-mode output voltage | RL = 54 Ω or 100 Ω, see Figure 7-1 | -1 | +3 | V | ||
∆|VOC| | Change in magnitude of common-mode output voltage(3) | RL = 54 Ω or 100 Ω, see Figure 7-1 | ±0.2 | V | |||
IO | Output current | Output disabled(6) | VO = 12 V | 1 | mA | ||
VO = –7 V | –0.8 | ||||||
IIH | High-level input current | VI = 2.4 V | 20 | µA | |||
IIL | Low-level input current | VI = 0.4 V | –400 | µA | |||
IOS | Short-circuit output current | VO = –7 V | –250 | mA | |||
VO = 0 | –150 | ||||||
VO = VCC | 250 | ||||||
VO = 12 V | 250 | ||||||
ICC | Supply current (total package) | No load | Outputs enabled | 42 | 70 | mA | |
Outputs disabled | 26 | 35 |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIT+ | Positive-going input threshold voltage | VO = 2.7 V, IO = –0.4 mA | 0.2 | V | |||
VIT– | Negative-going input threshold voltage | VO = 0.5 V, IO = 8 mA | –0.2(2) | V | |||
Vhys | Input hysteresis voltage (VIT+ – VIT–) | 50 | mV | ||||
VIK | Enable Input clamp voltage | II = –18 mA | –1.5 | V | |||
VOH | High-level output voltage | VID = 200 mV, IOH = –400 µA, see Figure 7-2 | 2.7 | V | |||
VOL | Low-level output voltage | VID = –200 mV, IOL = 8 mA, see Figure 7-2 | 0.45 | V | |||
IOZ | High-impedance-state output current | VO = 0.4 V to 2.4 V | ±20 | µA | |||
II | Line input current | Other input = 0 V(3) | VI = 12 V | 1 | mA | ||
VI = –7 V | –0.8 | ||||||
IIH | High-level enable input current | VIH = 2.7 V | 20 | µA | |||
IIL | Low-level enable input current | VIL = 0.4 V | –100 | µA | |||
rI | Input resistance | VI = 12 V | 12 | kΩ | |||
IOS | Short-circuit output current | –15 | –85 | mA | |||
ICC | Supply current (total package) | No load | Outputs enabled | 42 | 55 | mA | |
Outputs disabled | 26 | 35 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
td(OD) | Differential-output delay time | RL = 54 Ω, see Figure 7-3 | 15 | 22 | ns | |
tt(OD) | Differential-output transition time | RL = 54 Ω, see Figure 7-3 | 20 | 30 | ns | |
tPZH | Output enable time to high level | See Figure 7-4 | 85 | 120 | ns | |
tPZL | Output enable time to low level | See Figure 7-5 | 40 | 60 | ns | |
tPHZ | Output disable time from high level | See Figure 7-4 | 150 | 250 | ns | |
tPLZ | Output disable time from low level | See Figure 7-5 | 20 | 30 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH | Propagation delay time, low- to high-level output | VID = 0 to 3 V, see Figure 7-6 | 21 | 35 | ns | |
tPHL | Propagation delay time, high- to low-level output | 23 | 35 | |||
tPZH | Output enable time to high level | See Figure 7-7 | 10 | 20 | ns | |
tPZL | Output enable time to low level | 12 | 20 | |||
tPHZ | Output disable time from high level | See Figure 7-7 | 20 | 35 | ns | |
tPLZ | Output disable time from low level | 17 | 25 |
Only the 0°C to 70°C portion of the curve applies to the SN75176B device. |
The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. They are designed for balanced transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27.
The SN65176B and SN75176B devices combine a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or VCC = 0. These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications.
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 kΩ, an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B devices can be used in transmission-line applications employing the SN75172 and SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.