该器件包含两个独立的 D 型正缘触发触发器。所有输入均包括施密特触发,可实现慢速或高噪声输入信号。将预设 (PRE) 输入设为低电平,会输出高电平。将清零 (CLR) 输入设为低电平,会重新输出低电平。预设和清零功能是异步的,并且不依赖于其他输入的电平。当 PRE 和 CLR 处于非活动状态(高电平)时,数据 (D) 输入处满足设置时间要求的数据将传输到时钟 (CLK) 脉冲正向缘上的输出(Q,Q)处。时钟触发在一定电压电平下发生,并且不与输入 (CLK) 信号的上升时间直接相关。经过保持时间间隔后,可以更改数据 (D) 输入处的数据而不影响输出(Q,Q)处的电平。
器件型号 | 封装(1) | 封装尺寸(标称值) |
---|---|---|
SN74HCS74PW-Q1 | TSSOP (14) | 5.00mm × 4.40mm |
SN74HCS74D-Q1 | SOIC (14) | 8.70mm × 3.90mm |
SN74HCS74BQA-Q1 | WQFN (14) | 3.00mm × 2.50mm |
SN74HCS74DYY-Q1 | SOT-23-THIN (14) | 2.00 mm x 4.20 mm |
Changes from Revision D (March 2021) to Revision E (December 2021)
Changes from Revision C (November 2020) to Revision D (March 2021)
Changes from Revision B (August 2019) to Revision C (November 2020)
Changes from Revision A (June 2019) to Revision B (August 2019)
Changes from Revision * (April 2019) to Revision A (June 2019)
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
1 CLR | 1 | Input | Clear for channel 1, active low |
1D | 2 | Input | Data for channel 1 |
1CLK | 3 | Input | Clock for channel 1, rising edge triggered |
1 PRE | 4 | Input | Preset for channel 1, active low |
1Q | 5 | Output | Output for channel 1 |
1 Q | 6 | Output | Inverted output for channel 1 |
GND | 7 | — | Ground |
2 Q | 8 | Output | Inverted output for channel 2 |
2Q | 9 | Output | Output for channel 2 |
2 PRE | 10 | Input | Preset for channel 2, active low |
2CLK | 11 | Input | Clock for channel 2, rising edge triggered |
2D | 12 | Input | Data for channel 2 |
2 CLR | 13 | Input | Clear for channel 2, active low |
VCC | 14 | — | Positive supply |
Thermal Pad(1) | — | The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.5 | 7 | V | |
IIK | Input clamp current(2) | VI < –0.5 V or VI > VCC + 0.5 V | ±20 | mA | |
IOK | Output clamp current(2) | VI < –0.5 V or VI > VCC + 0.5 V | ±20 | mA | |
IO | Continuous output current | VO = 0 to VCC | ±35 | mA | |
Continuous current through VCC or GND | ±70 | mA | |||
TJ | Junction temperature(3) | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 2 | ±4000 | V |
Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C6 | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC | Supply voltage | 2 | 5 | 6 | V |
VI | Input voltage | 0 | VCC | V | |
VO | Output voltage | 0 | VCC | V | |
TA | Ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | SN74HCS74-Q1 | UNIT | ||||
---|---|---|---|---|---|---|
PW (TSSOP) | D (SOIC) | BQA (WQFN) | DYY (SOT) | |||
14 PINS | 14 PINS | 14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 151.7 | 133.6 | 109.7 | 236.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 79.4 | 89.0 | 111.0 | 143.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 94.7 | 89.5 | 77.9 | 146.0 | °C/W |
ΨJT | Junction-to-top characterization parameter | 25.2 | 45.5 | 20.2 | 29.5 | °C/W |
ΨJB | Junction-to-board characterization parameter | 94.1 | 89.1 | 77.8 | 145.6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | 56.6 | N/A | °C/W |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
VT+ | Positive switching threshold | 2 V | 0.7 | 1.5 | V | |||
4.5 V | 1.7 | 3.15 | ||||||
6 V | 2.1 | 4.2 | ||||||
VT- | Negative switching threshold | 2 V | 0.3 | 1.0 | V | |||
4.5 V | 0.9 | 2.2 | ||||||
6 V | 1.2 | 3.0 | ||||||
ΔVT | Hysteresis (VT+ - VT-)(1) | 2 V | 0.2 | 1.0 | V | |||
4.5 V | 0.4 | 1.4 | ||||||
6 V | 0.6 | 1.6 | ||||||
VOH | High-level output voltage | VI = VIH or VIL | IOH = -20 µA | 2 V to 6 V | VCC – 0.1 | VCC – 0.002 | V | |
IOH = -6 mA | 4.5 V | 4.0 | 4.3 | |||||
IOH = -7.8 mA | 6 V | 5.4 | 5.75 | |||||
VOL | Low-level output voltage | VI = VIH or VIL | IOL = 20 µA | 2 V to 6 V | 0.002 | 0.1 | V | |
IOL = 6 mA | 4.5 V | 0.18 | 0.30 | |||||
IOL = 7.8 mA | 6 V | 0.22 | 0.33 | |||||
II | Input leakage current | VI = VCC or 0 | 6 V | ±100 | ±1000 | nA | ||
ICC | Supply current | VI = VCC or 0, IO = 0 | 6 V | 0.1 | 2 | µA | ||
Ci | Input capacitance | 2 V to 6 V | 5 | pF | ||||
Cpd | Power dissipation capacitance per gate | No load | 2 V to 6 V | 10 | pF |
PARAMETER | FROM (INPUT) | TO (OUTPUT) | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|---|
fmax | Max switching frequency | 2 V | 18 | 31 | MHz | |||
4.5 V | 45 | 95 | ||||||
6 V | 65 | 105 | ||||||
tpd | Propagation delay | PRE or CLR | Q or Q | 2 V | 19 | 42 | ns | |
4.5 V | 8 | 19 | ||||||
6 V | 7 | 15 | ||||||
CLK | Q or Q | 2 V | 19 | 42 | ns | |||
4.5 V | 8 | 19 | ||||||
6 V | 7 | 15 | ||||||
tt | Transition-time | Q or Q | 2 V | 9 | 16 | ns | ||
4.5 V | 5 | 9 | ||||||
6 V | 4 | 8 |
PARAMETER | VCC | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
fclock | Clock frequency | 2 V | 18 | MHz | ||
4.5 V | 45 | |||||
6 V | 65 | |||||
tw | Pulse duration | PRE or CLR low | 2 V | 11 | ns | |
4.5 V | 11 | |||||
6 V | 11 | |||||
CLK high or low | 2 V | 14 | ns | |||
4.5 V | 12 | |||||
6 V | 11 | |||||
tsu | Setup time before CLK high | Data | 2 V | 24 | ns | |
4.5 V | 9 | |||||
6 V | 6 | |||||
PRE or CLR inactive | 2 V | 7 | ns | |||
4.5 V | 5 | |||||
6 V | 5 | |||||
th | Hold time | Data after CLK↑ | 2 V | 0 | ns | |
4.5 V | 0 | |||||
6 V | 0 |