ZHCSDW4D February   2011  – September 2022 SN74GTL2003

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Provides Bidirectional Voltage Translation With No Direction Control Required
      2. 8.3.2 Flow Through Pinout
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Bidirectional Translation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Sizing Pullup Resistors
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Unidirectional Down Translation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Sizing Pullup Resistors
      3. 9.2.3 Unidirectional Up Translation
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Sizing Pullup Resistors
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.4 Device Functional Modes

Table 8-1 High to Low Translation
(Assuming Dn is at the Higher Voltage Level)
GREF(1)DREFSREFINPUTS
D8–D1		OUTPUT S8–S1TRANSISTOR
HH0 VXXOff
HHVTT(2)HVTT(3)On
HHVTTLL(4)On
LL0 – VTTXXOff
(1) GREF should be at least 1.5 V higher than SREF for best translator operation.
(2) VTT is equal to the SREF voltage.
(3) Sn is not pulled up or pulled down.
(4) Sn follows the Dn input LOW.
Table 8-2 Low to High Translation
(Assuming Dn is at the Higher Voltage Level)
GREF(1)DREFSREFINPUTS
D8–D1		OUTPUT S8–S1TRANSISTOR
HH0 VXXOff
HHVTT(2)VTTH(3)Nearly Off
HHVTTLL(4)On
LL0 – VTTXXOff
(1) GREF should be at least 1.5 V higher than SREF for best translator operation.
(2) VTT is equal to the SREF voltage.
(3) Dn is pulled up to VCC through an external resistor.
(4) Dn follows the Sn input LOW.