SCES644D MARCH   2006  – December 2015 SN74AUP1G74

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, TA = 25°C
    6. 6.6  Electrical Characteristics, TA = -40°C to +85°C
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics, CL = 5 pF
    9. 6.9  Switching Characteristics, CL = 10 pF
    10. 6.10 Switching Characteristics, CL = 15 pF
    11. 6.11 Switching Characteristics, CL = 30 pF
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information 
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width)
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Power Button Circuit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8 Detailed Description

8.1 Overview

This single positive-edge-triggered D-type flip-flop is designed for 0.8-V to 3.6-V VCC operation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. When both the CLR and PRE inputs are set low, the CLR input will override the PRE input.

NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

SN74AUP1G74 ls_ces644.gif
Pin numbers shown are for the DCU and DQE packages

8.3 Feature Description

This device is available in the Texas Instrument's NanoStar package. It has low static-power consumption of
0.9 uA maximum. It has low noise with overshoot and undershoot at less than ten percent of VCC. It supports partial-power-down mode operation, which is specified by Ioff. The Schmitt-trigger inputs allow for slow or noisy input signals. The device has a wide operating voltage range of 0.8 V to 3.6 V, and is optimized for 3.3 V. It has low propagation delay of 5 ns maximum at 3.3 V.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SN74AUP1G74.

Table 1. Function Table

INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
X L X X L H
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q 0