ZHCSJD7C April 2002 – February 2019 SN65LVDT14 , SN65LVDT41
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
In typical SPI communication, the SPI master decides the sampling rate and data transfer rate, sends data at the rising edge of one clock cycle, and receives data on the falling edge within the same clock cycle. In a low latency system, the data in peripheral device should be made available to the host system with minimum delay. However in systems with high latency, the total round trip propagation delay of the SPI system must be less than half the SCLK period to avoid missing bits. There are three major delay contributors in a typical system—the SPI peripheral, data link device, and transmission media. Both the SPI peripheral and the data link device have fixed delay. The delay in transmission media, however, increases as communication distance increases. The relationship between cable length and SPI clock frequency can be seen in Figure 22. Figure 22 refers to a system where both MISO and MOSI are used, accounting for the case of slave-to-mater data transmission, including roundtrip delay. The specific setup is described in Extending SPI and McBSP with differential interface products (SLLA142)