ZHCSE57A September   2015  – November 2015 RF430CL331H

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 典型应用
  2. 2修订历史记录
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Connections for Unused Pins
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Recommended Operating Conditions, Resonant Circuit
    5. 4.5 Supply Currents
    6. 4.6 Electrical Characteristics, Digital Inputs
    7. 4.7 Electrical Characteristics, Digital Outputs
    8. 4.8 Thermal Characteristics
    9. 4.9 Timing and Switching Characteristics
      1. 4.9.1 Reset Timing
      2. 4.9.2 Serial Communication Protocol Timing
      3. 4.9.3 RF143B NFC/RFID Analog Front End
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Terms and Acronyms
    4. 5.4  Serial Communication Interface
    5. 5.5  Communication Protocol
    6. 5.6  I2C Protocol
      1. 5.6.1 I2C Examples
        1. 5.6.1.1 I2C Write
        2. 5.6.1.2 I2C Read
      2. 5.6.2 BIP-8 Communication Mode With I2C
    7. 5.7  NFC Type 4B Tag Platform
      1. 5.7.1 ISO/IEC 14443-3 Commands
      2. 5.7.2 NFC Tag Type 4 Commands
      3. 5.7.3 Data Rate Settings
    8. 5.8  NDEF Structure
    9. 5.9  Typical Operation
      1. 5.9.1 NDEF or Capability Container Select Procedure
      2. 5.9.2 NDEF or Capability Container Read Binary Procedure
        1. 5.9.2.1 NDEF Read Command Internal Buffer Handling
        2. 5.9.2.2 NDEF Read Command Internal Buffer Handling (With Caching)
      3. 5.9.3 NDEF or Capability Container Read Procedure (Prefetch Feature)
        1. 5.9.3.1 NDEF Read Command With Prefetch Internal Buffer Handling
      4. 5.9.4 NDEF or Capability Container Write Procedure (Blocking)
        1. 5.9.4.1 NDEF Write Command (Blocking) Internal Buffer Handling
      5. 5.9.5 NDEF or Capability Container Write Procedure (Nonblocking)
        1. 5.9.5.1 NDEF Write Procedure (Nonblocking) Internal Buffer Handling
    10. 5.10 RF Command Response Timing Limits
    11. 5.11 Registers
      1. 5.11.1  General Control Register
      2. 5.11.2  Status Register
      3. 5.11.3  Interrupt Registers
      4. 5.11.4  CRC Registers
      5. 5.11.5  Communication Watchdog Register
      6. 5.11.6  Version Register
      7. 5.11.7  NDEF File Identifier Register
      8. 5.11.8  Host Response Register
      9. 5.11.9  NDEF Block Length Register
      10. 5.11.10 NDEF File Offset Register
      11. 5.11.11 Buffer Start Register
      12. 5.11.12 SWTX Register
      13. 5.11.13 Custom Status Word Response Register
    12. 5.12 Identification
      1. 5.12.1 Revision Identification
      2. 5.12.2 Device Identification
      3. 5.12.3 JTAG Identification
      4. 5.12.4 Software Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Diagram
    2. 6.2 References
  7. 7器件和文档支持
    1. 7.1 器件支持
      1. 7.1.1 开发支持
        1. 7.1.1.1 入门和下一步
      2. 7.1.2 器件和开发工具命名规则
    2. 7.2 文档支持
      1. 7.2.1 相关文档　
    3. 7.3 社区资源
    4. 7.4 商标
    5. 7.5 静电放电警告
    6. 7.6 出口管制提示
    7. 7.7 Glossary
  8. 8机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 Terminal Configuration and Functions

3.1 Pin Diagrams

Figure 3-1 shows the pinout for the 14-pin PW package.

RF430CL331H pinout_pw14_331A_slase18.gif Figure 3-1 14-Pin PW Package (Top View)

Figure 3-2 shows the pinout for the 16-pin RGT package.

RF430CL331H pinout_rgt16_slase18.gif Figure 3-2 16-Pin RGT Package (Top View)

3.2 Pin Attributes

Table 3-1 Pin Attributes

PIN NUMBER SIGNAL NAME SIGNAL TYPE (1) BUFFER TYPE (2) POWER SOURCE RESET STATE (3)
PW RGT
1 15 VCC PWR Power VCC N/A
2 1 ANT1 RF Analog – N/A
3 2 ANT2 RF Analog – N/A
4 3 RST I LVCMOS VCC PU
5 4 E0 I LVCMOS VCC OFF
6 5 E1 I LVCMOS VCC OFF
7 6 E2 I LVCMOS VCC OFF
8 7 INTO O LVCMOS VCC OFF
9 8 I2C_READY O LVCMOS VCC DRIVE1
10 9 I2C_SIGNAL O LVCMOS VCC DRIVE1
11 10 SCL I/O LVCMOS VCC OFF
12 11 SDA I/O LVCMOS VCC OFF
13 12 VCORE PWR Power VCC N/A
14 13 VSS PWR Power VCC N/A
– 14 NC – – – –
– 16 NC – – – –
(1) Signal Types: I = Input, O = Output, I/O = Input or Output, PWR = Power, RF = Radio frequency
(2) Buffer Types: See Table 3-3 for details.
(3) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
DRIVE0 = Drive output low
DRIVE1 = Drive output high
N/A = Not applicable

3.3 Signal Descriptions

Table 3-2 describes the signals.

Table 3-2 Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER I/O (1) DESCRIPTION
PW RGT
Power VCC 1 15 PWR 3.3-V power supply
VCORE 13 12 PWR Regulated core supply voltage
VSS 14 13 PWR Ground supply
RF ANT1 2 1 RF Antenna input 1
ANT2 3 2 RF Antenna input 2
Serial communication E0 5 4 I I2C address select 0
E1 6 5 I I2C address select 1
E2 7 6 I I2C address select 2
I2C_READY 9 8 O High indicates that I2C communication can be started. Low indicates that I2C communication must not be started.
I2C_SIGNAL 10 9 O Low indicates that a wait time extension command is automatically being sent. I2C communication does not have to be stopped.
SCL 11 10 I/O I2C clock
SDA 12 11 I/O I2C data
System INTO 8 7 O Interrupt output
RST 4 3 I Reset input (active low) (2)
No connect NC – 14
16		 – Leave open, no connection
(1) I = Input, O = Output, PWR = Power, RF = RF antenna
(2) With integrated pullup

3.4 Pin Multiplexing

None of the pins on this device are multiplexed.

Table 3-3 Buffer Type

BUFFER TYPE (STANDARD) NOMINAL VOLTAGE HYSTERESIS PU OR PD NOMINAL PU OR PD STRENGTH (µA) OUTPUT DRIVE STRENGTH (mA) OTHER CHARACTERISTICS
LVCMOS 3.3 V Y N/A See Section 4.6, Electrical Characteristics, Digital Inputs See Section 4.7, Electrical Characteristics, Digital Outputs
Analog, RF 3.3 V N N/A N/A N/A See analog modules in Section 4, Specifications, for details
Power 3.3 V Y with SVS on N/A N/A N/A

3.5 Connections for Unused Pins

Leave no connect (NC) pins unconnected.

Leave unused outputs unconnected.

Drive or pull unused inputs high or low.