SBOS392I August   2007  – April 2026

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Thermal Hysteresis
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-Up Time
      2. 8.3.2 Low Temperature Drift
      3. 8.3.3 Power Dissipation
      4. 8.3.4 Noise Performance
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 REF3312 in a Bipolar Signal-Chain Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Op Amp Level-Shift Design
          2. 9.2.1.2.2 Differential Input Attenuator Design
          3. 9.2.1.2.3 Input Filtering
          4. 9.2.1.2.4 Component Selection
            1. 9.2.1.2.4.1 Voltage References
            2. 9.2.1.2.4.2 Op Amp
          5. 9.2.1.2.5 Input Attenuation and Level Shifting
          6. 9.2.1.2.6 Input Filtering
          7. 9.2.1.2.7 Passive Component Tolerances and Materials
        3. 9.2.1.3 Application Curves
          1. 9.2.1.3.1 DC Performance
          2. 9.2.1.3.2 AC Performance
    3. 9.3 Power-Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.2.1.2.2 Differential Input Attenuator Design

VDIFF is the difference between the two inputs, as shown in Equation 9:

Equation 9. V D I F F = A 1 + - A 1 - = R 3 R 2 + R 3 V R E F + R 2 ∥ R 3 R 1 V I N - V R E F 2

When the ratio of R3 and R2 equals the ratio of R7 and R6, Equation 9 simplifies to Equation 11.

That is, if:

Equation 10. R 3 R 2 + R 3 V R E F = R 7 R 6 + R 7 V R E F = 1 2 V R E F

Then:

Equation 11. V D I F F = R 2 ∥ R 3 R 1 V I N

Determine the ratio of R1, R2, and R3 by setting A1+ equal to the maximum VDIFF for a full-scale positive or negative input voltage, VIN_MAX, as shown in Equation 12:

Equation 12. A 1 + = V D I F F _ M A X = R 2 ∥ R 3 R 1 V I N _ M A X

R2 equals R3; therefore, Equation 12 simplifies to R2 / 2, resulting in Equation 13:

Equation 13. V D I F F _ M A X = R 2 2 × R 1 V I N _ M A X