ZHCSDH3
November 2014
PCM5252
PRODUCTION DATA.
1
特性
2
应用
3
说明
4
修订历史记录
5
Device Comparison
6
Pin Configuration and Functions
6.1
Control Mode Effect On Pin Assignments
6.2
Pin Assignments
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Switching Characteristics
7.7
Timing Requirements: SCK Input
7.8
Timing Requirements: PCM Audio Data
7.9
Timing Requirements: I2S Master, See
7.10
Timing Requirements: XSMT
7.11
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Terminology
8.3.2
Audio Data Interface
8.3.2.1
Audio Serial Interface
8.3.2.2
PCM Audio Data Formats
8.3.2.3
Zero Data Detect
8.3.3
XSMT Pin (Soft Mute / Soft Un-Mute)
8.3.4
Audio Processing
8.3.4.1
PCM5252 Audio Processing Options
8.3.4.1.1
Overview
8.3.4.1.2
miniDSP Instruction Register
8.3.4.1.3
Digital Output
8.3.4.1.4
Software
8.3.4.2
Interpolation Filter
8.3.4.3
Overview
8.3.4.4
Smart SOA
8.3.4.5
Smart BASS
8.3.4.6
Smart Protection
8.3.4.7
Implementing a Real World Design
8.3.4.8
Digital Output
8.3.4.9
Software
8.3.4.10
Process Flow
8.3.5
DAC and Differential Analog Outputs
8.3.5.1
Analog Outputs
8.3.5.2
Choosing Between VREF and VCOM Modes
8.3.5.2.1
Voltage Reference and Output Levels
8.3.5.2.2
Mode Switching Sequence, from VREF Mode to VCOM Mode
8.3.5.3
Digital Volume Control
8.3.5.3.1
Emergency Ramp-Down
8.3.5.4
Analog Gain Control
8.3.6
Reset and System Clock Functions
8.3.6.1
Clocking Overview
8.3.6.2
Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
8.3.6.3
Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
8.3.6.4
Clock Generation Using the PLL
8.3.6.5
PLL Calculation
8.3.6.5.1
Examples:
8.3.6.5.1.1
Recommended PLL Settings
8.3.6.6
Clock Master Mode from Audio Rate Master Clock
8.3.6.7
Clock Master from a Non-Audio Rate Master Clock
8.4
Device Functional Modes
8.4.1
Choosing a Control Mode
8.4.1.1
Software Control
8.4.1.1.1
SPI Interface
8.4.1.1.1.1
Register Read and Write Operation
8.4.1.1.2
I2C Interface
8.4.1.1.2.1
Slave Address
8.4.1.1.2.2
Register Address Auto-Increment Mode
8.4.1.1.2.3
Packet Protocol
8.4.1.1.2.4
Write Register
8.4.1.1.2.5
Read Register
8.4.1.1.2.6
Timing Characteristics
8.4.2
VREF and VCOM Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
High Fidelity Smartphone Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Initialization Script
9.2.1.3
Application Performance Plot
10
Power Supply Recommendations
10.1
Power Supply Distribution and Requirements
10.2
Recommended Powerdown Sequence
10.2.1
XSMT = 0
10.2.2
Clock Error Detect
10.2.3
Planned Shutdown
10.2.4
Unplanned Shutdown
10.3
External Power Sense Undervoltage Protection Mode
10.4
Power-On Reset Function
10.4.1
Power-On Reset, DVDD 3.3-V Supply
10.4.2
Power-On Reset, DVDD 1.8-V Supply
10.5
PCM5252 Power Modes
10.5.1
Setting Digital Power Supplies and I/O Voltage Rails
10.5.2
Power Save Modes
10.5.3
Power Save Parameter Programming
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Programming
12.1
Coefficient Data Formats
12.2
Power Down and Reset Behavior
13
Register Maps
13.1
PCM5252 Register Map
13.1.1
Detailed Register Descriptions
13.1.1.1
Register Map Summary
13.1.1.2
Page 0 Registers
13.1.1.3
Page 1 Registers
13.1.1.4
Page 44 Registers
13.1.1.5
Page 253 Registers
13.1.2
PLL Tables for Software Controlled Devices
14
器件和文档支持
14.1
社区资源
14.2
商标
14.3
静电放电警告
15
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RHB|32
MPQF130D
散热焊盘机械数据 (封装 | 引脚)
RHB|32
QFND029X
订购信息
zhcsdh3_oa
4
修订历史记录
日期
修订版本
注释
2014 年 11 月
*
最初发布。