SLES254D April   2010  – July 2015 PCM1753-Q1 , PCM1754-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Clock Input Timing
    7. 7.7 Audio Interface Timing
    8. 7.8 Control Interface Timing Requirements
    9. 7.9 Typical Characteristics
      1. 7.9.1 Digital Filter (De-Emphasis Off)
      2. 7.9.2 Analog Dynamic Performance (Supply Voltage Characteristics)
      3. 7.9.3 Analog Dynamic Performance (Temperature Characteristics)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 System Clock and Reset Functions
        1. 8.3.1.1 System Clock Input
        2. 8.3.1.2 Power-On Reset Functions
      2. 8.3.2 Audio Serial Interface
        1. 8.3.2.1 Audio Data Formats and Timing
      3. 8.3.3 Zero Flag (PCM1754-Q1)
      4. 8.3.4 Zero Flag (PCM1753-Q1)
      5. 8.3.5 Zero Flag Outputs
      6. 8.3.6 Analog Outputs
        1. 8.3.6.1 VCOM Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control (PCM1754-Q1)
      2. 8.4.2 Oversampling Rate Control (PCM1754-Q1)
    5. 8.5 Programming
      1. 8.5.1 Software Control (PCM1753-Q1)
        1. 8.5.1.1 Register Write Operation
    6. 8.6 Register Maps
      1. 8.6.1 Mode Control Registers (PCM1753-Q1)
        1. 8.6.1.1 User-Programmable Mode Controls
        2. 8.6.1.2 Register Definitions
          1. 8.6.1.2.1  ATx[7:0]: Digital Attenuation Level Setting
          2. 8.6.1.2.2  MUTx: Soft Mute Control
          3. 8.6.1.2.3  OVER: Oversampling Rate Control
          4. 8.6.1.2.4  SRST: Reset
          5. 8.6.1.2.5  DACx: DAC Operation Control
          6. 8.6.1.2.6  DM12: Digital De-Emphasis Function Control
          7. 8.6.1.2.7  DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
          8. 8.6.1.2.8  FMT[2:0]: Audio Interface Data Format
          9. 8.6.1.2.9  FLT: Digital Filter Rolloff Control
          10. 8.6.1.2.10 DREV: Output Phase Select
          11. 8.6.1.2.11 ZREV: Zero Flag Polarity Select
          12. 8.6.1.2.12 AZRO: Zero Flag Function Select
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Supplies and Grounding
        2. 9.2.1.2 DAC Output Filter Circuits
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Total Harmonic Distortion + Noise
        2. 9.2.2.2 Dynamic Range
        3. 9.2.2.3 Idle Channel Signal-to-Noise Ratio (SNR)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VCC –0.3 6.5 V
Ground voltage differences AGND, DGND –0.1 0.1 V
Input voltage –0.3 6.5 V
Input current (any pins except supplies) –10 10 mA
Ambient temperature under bias –40 105 °C
Junction temperature 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100–002(1) ±2000 V
Charged device model (CDM), per AEC Q100–011 Corner pins (1, 8, 9, and 16) ±750
Other pins ±500
(1) AEC Q100–002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS–001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Voltage range 4.5 5 5.5 VDC

7.4 Thermal Information

THERMAL METRIC(1) PCM175x-Q1 UNIT
DBQ (SSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 111.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.4 °C/W
RθJB Junction-to-board thermal resistance 55.1 °C/W
ψJT Junction-to-top characterization parameter 13.5 °C/W
ψJB Junction-to-board characterization parameter 54.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
DATA FORMAT
fS Sampling frequency 5 200 kHz
System clock frequency(3) 128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1152 fS		 kHz
DIGITAL INPUT/OUTPUT
Logic family TTL compatible
VIH Input logic level, high 2 VDC
VIL Input logic level, low 0.8
IIH Input logic current, high (SCK, BCK, DATA, and LRCK pins) VIN = VCC 10 µA
IIL Input logic current, low (SCK, BCK, DATA, and LRCK pins) VIN = 0 V –10 µA
IIH Input logic current, high (TEST, DEMP, MUTE, and FMT pins) VIN = VCC 65 100 µA
IIL Input logic current, low (TEST, DEMP, MUTE, and FMT pins) VIN = 0 V –10 µA
VOH Output logic level, high (ZEROA pin) IOH = –1 mA 2.4 VDC
VOL Output logic level, low (ZEROA pin) IOL = 1 mA 0.4 VDC
DYNAMIC PERFORMANCE(1)(2)
THD+N at VOUT = 0 dB fS = 44.1 kHz 0.00% 0.01%
fS = 96 kHz 0.00%
fS = 192 kHz 0.00%
THD+N at VOUT = -60 dB fS = 44.1 kHz 0.65%
fS = 96 kHz 0.80%
fS = 192 kHz 0.95%
Dynamic range EIAJ, A-weighted, fS = 44.1 kHz 100 106 dB
A-weighted, fS = 96 kHz 104
A-weighted, fS = 192 kHz 102
Signal-to-noise ratio EIAJ, A-weighted, fS = 44.1 kHz 100 106 dB
A-weighted, fS = 96 kHz 104
A-weighted, fS = 192 kHz 102
Channel separation fS = 44.1 kHz 97 103 dB
fS = 96 kHz 101
fS = 192 kHz 100
Level linearity error VOUT = -90 dB ±0.5 dB
DC ACCURACY
Gain error ±1 ±6 % of FSR
Gain mismatch, channel-to-channel ±1 ±3 % of FSR
Bipolar zero error VOUT = 0.5 VCC at BPZ ±30 ±60 mV
ANALOG OUTPUT
Output voltage Full scale (0 dB) 80% of VCC VPP
Center voltage 50% of VCC VDC
Load impedance AC-coupled load 5 kΩ
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS (SHARP ROLLOFF)
Pass band ±0.04 dB 0.454 fS
Stop band 0.546 fs
Pass-band ripple ±0.04 dB
Stop-band attenuation Stop band = 0.546 fS –50 dB
ANALOG FILTER PERFORMANCE
Frequency response At 20 kHz –0.03 dB
At 44 kHz –0.20
POWER SUPPLY REQUIREMENTS(2)
VCC Voltage range 4.5 5 5.5 VDC
ICC Supply current fS = 44.1 kHz 16 21 mA
fS = 96 kHz 25
fS = 192 kHz 30
Power dissipation fS = 44.1 kHz 80 105 mW
fS = 96 kHz 125
fS = 192 kHz 150
TEMPERATURE RANGE
Operation temperature –40 105 °C
RθJA Thermal resistance 16-pin SSOP 115 °C/W
(1) Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in the averaging mode.
(2) Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS of register 18.
(3) System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, 1152 fS with auto detect.

7.6 System Clock Input Timing

For more information, see the System Clock Input section.
MIN NOM MAX UNIT
t(SCKH) System clock pulse duration, high See Figure 20. 7 ns
t(SCKL) System clock pulse duration, low 7 ns
t(SCY) System clock pulse cycle time See (1)  ns
(1) 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS

7.7 Audio Interface Timing

For more information, see the Audio Data Formats and Timing section.
MIN MAX UNIT
t(BCY) BCK pulse cycle time See Figure 22. 1/(32 fS)
1/(48 fS)
1/(64 fS)(1)		 ns
t(BCH) BCK high–level time 35 ns
t(BCL) BCK low–level time 35 ns
t(BL) BCK rising edge to LRCK edge 10 ns
t(LB) LRCK falling edge to BCK rising edge 10 ns
t(DS) DATA setup time 10 ns
t(DH) DATA hold time 10 ns
(1) fS is the sampling frequency (such as, 44.1 kHz, 48 kHz, 96 kHz, and so on).

7.8 Control Interface Timing Requirements

These timing parameters are critical for proper control port operation.
MIN NOM MAX UNIT
t(MCY) MC pulse cycle time See Figure 1. 100 ns
t(MCL) MC low-level time 50 ns
t(MCH) MC high-level time 50 ns
t(MCH) ML high-level time See (2) ns
t(MLS) ML falling edge to MC rising edge 20 ns
t(MLH) ML hold time(1) 20 ns
t(MDH) MD hold time 15 ns
t(MDS) MD setup time 20 ns
(1) MC rising edge for LSB to ML rising edge.
(2) PCM1753-Q1 PCM1754-Q1 eq_timing_sles254.gif seconds (min); fS: sampling rate.
PCM1753-Q1 PCM1754-Q1 sftwarectrl_03.gifFigure 1. Control Interface Timing

7.9 Typical Characteristics

7.9.1 Digital Filter (De-Emphasis Off)

All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
PCM1753-Q1 PCM1754-Q1 g_freq_respons_sharp_rolloff_les254.gif
Frequency response Sharp rolloff
Figure 2. Amplitude vs Frequency
PCM1753-Q1 PCM1754-Q1 g_freq_respons_slow_rolloff_les254.gif
Frequency response Slow rolloff
Figure 4. Amplitude vs Frequency
PCM1753-Q1 PCM1754-Q1 g_deemphasis_level_freq_32khz_les254.gif
fS = 32 kHz
Figure 6. De-Emphasis Level vs Frequency
PCM1753-Q1 PCM1754-Q1 g_deemphasis_level_freq_44p1khz_les254.gif
fS = 44.1 kHz
Figure 8. De-Emphasis Level vs Frequency
PCM1753-Q1 PCM1754-Q1 g_deemphasis_level_freq_48khz_les254.gif
fS = 48 kHz
Figure 10. De-Emphasis Level vs Frequency
PCM1753-Q1 PCM1754-Q1 g_passband_ripple_sharp_rolloff_les254.gif
Pass-band ripple Sharp rolloff
Figure 3. Amplitude vs Frequency
PCM1753-Q1 PCM1754-Q1 g_transition_chars_slow_rolloff_les254.gif
Transition characteristics Slow rolloff
Figure 5. Amplitude vs Frequency
PCM1753-Q1 PCM1754-Q1 g_deemphasis_error_freq_32khz_les254.gif
fS = 32 kHz
Figure 7. De-Emphasis Error vs Frequency
PCM1753-Q1 PCM1754-Q1 g_deemphasis_error_freq_44p1khz_les254.gif
fS = 44.1 kHz
Figure 9. De-Emphasis Error vs Frequency
PCM1753-Q1 PCM1754-Q1 g_deemphasis_error_freq_48khz_les254.gif
fS = 48 kHz
Figure 11. De-Emphasis Error vs Frequency

7.9.2 Analog Dynamic Performance (Supply Voltage Characteristics)

All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
PCM1753-Q1 PCM1754-Q1 g_thdn_vcc_les254.gifFigure 12. Total Harmonic Distortion + Noise vs Supply Voltage
PCM1753-Q1 PCM1754-Q1 g_snr_vcc_les254.gifFigure 14. Signal-to-Noise Ratio vs Supply Voltage
PCM1753-Q1 PCM1754-Q1 g_dynamic_range_vcc_les254.gifFigure 13. Dynamic Range vs Supply Voltage
PCM1753-Q1 PCM1754-Q1 g_channel_separation_vcc_les254.gifFigure 15. Channel Separation vs Supply Voltage

7.9.3 Analog Dynamic Performance (Temperature Characteristics)

All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
PCM1753-Q1 PCM1754-Q1 g_thdn_temp_les254.gifFigure 16. Total Harmonic Distortion + Noise vs Free-Air Temperature
PCM1753-Q1 PCM1754-Q1 g_snr_temp_les254.gifFigure 18. Signal-to-Noise Ratio vs Free-Air Temperature
PCM1753-Q1 PCM1754-Q1 g_dynamic_range_temp_les254.gifFigure 17. Dynamic Range vs Free-Air Temperature
PCM1753-Q1 PCM1754-Q1 g_channel_separation_temp_les254.gifFigure 19. Channel Separation vs Free-Air Temperature